Method of forming stacked dies

• US 8,158,456 B2
• Filed: 12/05/2008
• Issued: 04/17/2012
• Est. Priority Date: 12/05/2008
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chen, Ming-Fa, Chen, Chen-Shien, Chiu, Wen-Chih
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US12/329,341
• Publication Number:
  US 20100144094A1
• Time in Patent Office: 1,229 Days
• Field of Search: 438/614, 438/620, 438/109, 438/459
• US Class Current: 438/109
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68327 used during dicing or grinding
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2224/03 Manufacturing methods
• CPC Class Codes: H01L 2224/034 by blanket deposition of the material of the bonding area
• CPC Class Codes: H01L 2224/0361 Physical or chemical etching
• CPC Class Codes: H01L 2224/03616 Chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05572 the external layer extending out of an opening
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05684 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/11 Manufacturing methods
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13116 : Lead [Pb] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/1403 : Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16146 : the bump connector connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/80 : Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
• CPC Class Codes: H01L 2224/81 : using a bump connector
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2224/9202 : Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9222 : Sequential connecting processes
• CPC Class Codes: H01L 2224/92222 : the first connecting process involving a bump connector
• CPC Class Codes: H01L 2224/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 24/92 : Specific sequence of method steps
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0105 : Tin [Sn]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

The formation of through silicon vias (TSVs) in an integrated circuit (IC) die or wafer is described in which the TSV is formed in the integration process prior to metallization processing. TSVs may be fabricated with increased aspect ratio, extending deeper in a wafer substrate. The method generally reduces the risk of overly-thinning a wafer substrate in a wafer back-side grinding process typically used to expose and make electrical contacts to the TSVs. By providing deeper TSVs and bonding pads, individual wafers and dies may be bonded directly between the TSVs and bonding pads on an additional wafer.

Claims

1. A method of fabricating a stacked integrated circuit (IC) semiconductor die comprising:

forming one or more recesses in a first semiconductor wafer, the first semiconductor wafer having CMOS devices formed thereon;

filling the one or more recesses with conducting material to form one or more through-silicon vias in the first semiconductor wafer;

forming one or more bonding contacts on a front-side of the first semiconductor wafer;

attaching the front-side of the first semiconductor wafer to a carrier, exposing a back-side of the first semiconductor wafer, wherein the carrier provides mechanical support to the first semiconductor wafer in a subsequent back-side thinning process;

thinning the back-side of the first semiconductor wafer until the one or more through-silicon vias are exposed and slightly protrude the back-side; and

aligning and bonding the one or more through-silicon vias with corresponding one or more bonding contacts on one or more bonding surfaces on a second semiconductor die or wafer.

2. The method of claim 1, wherein the one or more recesses have a diameter from about 3 microns to about 50 microns and an aspect ratio from about 12:

1 to about 3;

1.

3. The method of claim 1, further comprising:

forming one or more semiconductor devices in the first semiconductor wafer;

forming an inter-layer dielectric (ILD) layer on the first semiconductor wafer;

forming one or more contact pads in the ILD layer making electrical contact to the one or more through-silicon vias;

forming interconnect metal traces in an inter-metal dielectric (IMD) layer over the ILD layer, the metal traces being electrically connected to the one or more semiconductor devices and the one or more contact pads in the ILD layer; and

forming a top dielectric layer having the one or more bonding contacts, the one or more bonding contacts being electrically coupled to one or more of the metal traces.

4. The method of claim 3, wherein the one or more contact pads are coupled to the one or more through-silicon vias through a redistribution conductive layer.

5. The method of claim 3, wherein the step of forming one or more recesses precedes the step of forming the one or more semiconductor devices.

6. The method of claim 3, wherein the step of forming one or more recesses precedes the step of forming interconnect metal traces.

7. The method of claim 1, wherein the conducting material used to form the one or more through-silicon vias is selected from the group consisting of:

copper, tungsten, aluminum, gold, silver, and combinations thereof.

8. The method of claim 1, wherein after the step of thinning, the first semiconductor wafer has a thickness of from about 15 microns to about 250 microns.

9. The method of claim 1, further comprising:

forming a metallization insulator layer on the back-side of the first semiconductor wafer after the step of thinning; and

forming second one or more bonding pads in the metallization insulator layer, wherein the second one or more bonding pads are electrically connected to the one or more through-silicon vias and slightly protrude the metallization insulator layer.

10. The method of claim 9, wherein the second one or more bonding pads are electrically coupled to the one or more through-silicon vias through a second redistribution conductive layer.

11. A method of fabricating a stacked integrated circuit (IC) semiconductor die comprising:

providing a first semiconductor wafer having one or more through-silicon vias formed in a substrate and having CMOS devices formed thereon;

attaching a front-side surface of the first semiconductor wafer to a carrier, exposing a back-side of the first semiconductor wafer, wherein the carrier provides mechanical support to the first semiconductor wafer in a subsequent back-side thinning;

thinning the back-side of the first semiconductor wafer until the one or more through-silicon vias are exposed and slightly protrude from the back-side;

forming one or more first bonding contacts in a metallization insulator layer over the thinned back-side of the first semiconductor wafer, the one or more first bonding contacts being electrically coupled to the one or more through-silicon vias;

providing a second semiconductor work-piece having one or more second bonding contacts on a bonding surface of the second semiconductor work-piece; and

aligning and bonding the one or more first bonding contacts on the first semiconductor wafer to the corresponding one or more second bonding contacts on the second semiconductor work-piece.

12. The method of claim 11, wherein the second semiconductor work-piece comprises a semiconductor wafer, and wherein the step of bonding results in a wafer-to-wafer bonding configuration.

13. The method of claim 11, wherein the second semiconductor work-piece comprises a semiconductor die, and wherein the step of bonding results in a die-to-wafer bonding configuration.

14. The method of claim 11, wherein the one or more through-silicon vias has a diameter from about 3 microns to about 50 microns and an aspect ratio from about 12:

1 to about 3;

1.

15. The method of claim 11, wherein after the step of thinning, the first semiconductor wafer has a thickness of from about 15 microns to about 250 microns.

16. The method of claim 11, wherein conducting material used to form the one or more through-silicon vias is selected from the group consisting of:

copper, tungsten, aluminum, gold, silver, and combinations thereof.

17. The method of claim 11, further comprising:

forming one or more semiconductor devices in the first semiconductor wafer; and

forming one or more second bonding contacts on the front-side of the first semiconductor wafer, the one or more second bonding contacts being electrically coupled to the one or more semiconductor devices and the one or more through-silicon vias through one or more interconnect metal traces in an inter-metal dielectric (IMD) layer over the first semiconductor wafer.

18. The method of claim 17, wherein forming the one or more semiconductor devices in the first semiconductor wafer are performed after the formation of the one or more through-silicon vias.

19. The method of claim 17, wherein forming the one or more semiconductor devices in the first semiconductor wafer are performed prior to the formation of the one or more interconnect metal traces.

20. The method of claim 17, further comprising:

bonding the one or more second bonding contacts on the stacked integrated circuit die to an IC package substrate through a plurality of bumps in a flip-chip IC packaging configuration.