Formation of TSV backside interconnects by modifying carrier wafers

• US 8,158,489 B2
• Filed: 03/31/2010
• Issued: 04/17/2012
• Est. Priority Date: 06/26/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Huang, Hon-Lin, Hsiao, Ching-Wen, Hsu, Kuo-Ching, Chen, Chen-Shien
• Primary Examiner(s): Geyer, Scott B
• Application Number:
  US12/751,512
• Publication Number:
  US 20100330798A1
• Time in Patent Office: 748 Days
• Field of Search: None
• US Class Current: 438/455
• CPC Class Codes: H01L 21/6836 Wafer tapes, e.g. grinding or dicing support tapes adhesive tapes in general C09J7/20
• CPC Class Codes: H01L 2221/6834 used to protect an active side of a device or wafer
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/54493 Peripheral marks on wafers, e.g. orientation flats, notches, lot number
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02351 comprising interlocking features
• CPC Class Codes: H01L 2224/02372 connecting to a via connection in the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05001 Internal layers
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05009 Bonding area integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05024 the internal layer being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05026 the internal layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/05548 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0557 : the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05571 : the external layer being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/05624 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05639 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/05644 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11002 : for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1147 : using a lift-off mask
• CPC Class Codes: H01L 2224/11901 : with repetition of the same manufacturing step
• CPC Class Codes: H01L 2224/13007 : Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13024 : the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1308 : being stacked
• CPC Class Codes: H01L 2224/13082 : Two-layer arrangements
• CPC Class Codes: H01L 2224/13083 : Three-layer arrangements
• CPC Class Codes: H01L 2224/13099 : Material
• CPC Class Codes: H01L 2224/131 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/13124 : Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 : Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13184 : Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/81193 : wherein the bump connectors are disposed on both the semiconductor or solid-state body and another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81801 : Soldering or alloying
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/544 : Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00013 : Fully indexed content
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01011 : Sodium [Na]
• CPC Class Codes: H01L 2924/01012 : Magnesium [Mg]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/0102 : Calcium [Ca]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01075 : Rhenium [Re]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/013 : Alloys
• CPC Class Codes: H01L 2924/01327 : Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/09701 : Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19043 : being a resistor
• CPC Class Codes: H01L 2924/3511 : Warping

Abstract

An integrated circuit structure includes a semiconductor wafer, which includes a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer. A carrier wafer is mounted onto the semiconductor wafer. The carrier wafer has a second notch overlapping at least a portion of the first notch. A side of the carrier wafer facing the semiconductor wafer forms a sharp angle with an edge of the carrier wafer. The carrier wafer has a resistivity lower than about 1×10⁸ Ohm-cm.

Claims

1. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor wafer comprising a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer, and a through-semiconductor via (TSV) extending into the semiconductor wafer;

mounting a carrier wafer onto the semiconductor wafer, wherein the carrier wafer comprises a second notch in the carrier wafer, and wherein the step of mounting the carrier wafer comprises overlapping at least a portion of the first notch with at least a portion of the second notch;

after the step of mounting the carrier wafer, grinding a backside of the semiconductor wafer to expose the TSV;

depositing a conductive layer on the backside of the semiconductor wafer and electrically connected to the TSV; and

after the step of depositing, demounting the carrier wafer from the semiconductor wafer.

2. The method of claim 1, wherein the second notch extends from an edge of the carrier wafer into the carrier wafer.

3. The method of claim 1, wherein the step of mounting the carrier wafer comprises aligning edges of the second notch to edges of the first notch.

4. The method of claim 1, wherein a portion of the second notch less than an entirety of the second notch overlaps an entirety of the first notch.

5. The method of claim 1, wherein a portion of the first notch less than an entirety of the first notch overlaps an entirety of the second notch.

6. The method of claim 1, wherein the semiconductor wafer comprises active devices, and wherein the carrier wafer comprises a glass wafer.

7. The method of claim 1, wherein substantially all corners of the carrier wafer on a side facing the semiconductor wafer have a sharp profile, and wherein the substantially all corners of the carrier wafer form 90 degree angles.

8. The method of claim 1, wherein the carrier wafer has a resistivity lower than about 1×

10⁸ Ohm-cm.

9. The method of claim 1, wherein a combined structure comprising the carrier wafer and the semiconductor wafer has a warpage of less than about 20 μ

m.

10. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor wafer comprising active devices, wherein the semiconductor wafer comprises a first notch extending from an edge of the of the semiconductor wafer into the semiconductor wafer; and

mounting a carrier wafer onto the semiconductor wafer, wherein the carrier wafer comprises a glass wafer, wherein the carrier wafer comprises a second notch, wherein the second notch overlaps at least a portion of the first notch, and wherein the carrier wafer is joined to the semiconductor wafer through an adhesive layer.

11. The method of claim 10 further comprising demounting the carrier wafer from the semiconductor wafer.

12. The method of claim 10, wherein the carrier wafer has a resistivity lower than about 1×

10⁸ Ohm-cm.

13. The method of claim 10, wherein a combined structure comprising the carrier wafer and the semiconductor wafer has a warpage of less than about 20 μ

m.

16. The method of claim 11, wherein the semiconductor wafer comprises a semiconductor substrate, and a through-semiconductor via (TSV) extending into the semiconductor substrate, and wherein the method further comprises, before the step of demounting the carrier wafer from the semiconductor substrate, forming an under-bump metallurgy (UBM) on a side of the semiconductor substrate and electrically connected to the TSV.

14. A method of forming an integrated circuit structure, the method comprising:

providing a semiconductor wafer; and

mounting a carrier wafer onto the semiconductor wafer, wherein substantially all corners of the carrier wafer on a side facing the semiconductor wafer have a sharp profile with a 90 degree angle, and wherein the carrier wafer has a resistivity lower than about 1×

10⁸ ohm.

15. The method of claim 14, wherein the semiconductor wafer comprises a first notch extending from an edge of the semiconductor wafer into the semiconductor wafer, and the carrier wafer comprises a second notch, and wherein the step of mounting the carrier wafer comprises aligning the second notch to overlap at least a portion of the first notch.