Structure and manufacturing method of a chip scale package
First Claim
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1. A chip package comprising:
- a substrate comprising a solder mask, a first contact point in a channel in said solder mask, a second contact point in said channel, wherein said first contact point is separate from said second contact point in said channel, wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, and an interconnect covered by said solder mask;
a semiconductor device comprising a polymer layer at a top of said semiconductor device and a metal pad having a third contact point at a bottom of an opening in said polymer layer;
a copper pillar between said third contact point and said substrate, wherein said copper pillar is connected to said third contact point through said opening, wherein said copper pillar has a thickness between 10 and 100 micrometers;
a solder between said copper pillar and said substrate, wherein said solder is connected to said copper pillar, wherein said solder electrically contacts said first contact point; and
an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill.
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Abstract
A new method and package is provided for the mounting of semiconductor devices that have been provided with small-pitch Input/Output interconnect bumps. Fine pitch solder bumps, consisting of pillar metal and a solder bump, are applied directly to the I/O pads of the semiconductor device, the device is then flip-chip bonded to a substrate. Dummy bumps may be provided for cases where the I/O pads of the device are arranged such that additional mechanical support for the device is required.
156 Citations
36 Claims
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1. A chip package comprising:
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a substrate comprising a solder mask, a first contact point in a channel in said solder mask, a second contact point in said channel, wherein said first contact point is separate from said second contact point in said channel, wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, and an interconnect covered by said solder mask; a semiconductor device comprising a polymer layer at a top of said semiconductor device and a metal pad having a third contact point at a bottom of an opening in said polymer layer; a copper pillar between said third contact point and said substrate, wherein said copper pillar is connected to said third contact point through said opening, wherein said copper pillar has a thickness between 10 and 100 micrometers; a solder between said copper pillar and said substrate, wherein said solder is connected to said copper pillar, wherein said solder electrically contacts said first contact point; and an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A chip package comprising:
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a substrate comprising a solder mask, a first contact point in a channel in said solder mask, a second contact point in said channel, wherein said first contact point is separate from said second contact point in said channel, wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, and an interconnect covered by said solder mask; a semiconductor device comprising a polymer layer at a top of said semiconductor device and a metal pad having a third contact point at a bottom of an opening in said polymer layer; a copper pillar between said third contact point and said substrate and over a top surface of said polymer layer, wherein said copper pillar is connected to said third contact point through said opening, wherein said copper pillar has a thickness between 10 and 100 micrometers; a titanium-containing layer between said third contact point and said copper pillar, wherein said titanium-containing layer is on said third contact point, on said top surface of said polymer layer and in said opening, wherein said copper pillar is connected to said third contact point through said titanium-containing layer; a solder between said copper pillar and said substrate, wherein said solder is connected to said copper pillar, wherein said solder electrically contacts said first contact point; a nickel-containing layer between said copper pillar and said solder, wherein said nickel-containing layer is connected to said copper pillar and said solder; and an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill. - View Dependent Claims (8, 9, 10, 11)
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12. A chip package comprising:
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a substrate comprising a solder mask, a first contact point in a channel in said solder mask, a second contact point in said channel, wherein said first contact point is separate from said second contact point in said channel, wherein said channel has a first sidewall and a second sidewall opposite to and substantially parallel with said first sidewall, and an interconnect covered by said solder mask; a semiconductor device comprising a passivation layer at a top of said semiconductor device and a metal pad having a third contact point at a bottom of an opening in said passivation layer; a copper pillar between said third contact point and said substrate, wherein said copper pillar is connected to said third contact point through said opening, wherein said copper pillar has a thickness between 10 and 100 micrometers; a solder between said copper pillar and said substrate, wherein said solder is connected to said copper pillar, wherein said solder electrically contacts said first contact point; and an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill. - View Dependent Claims (13, 14, 15, 16, 17)
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18. A chip package comprising:
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a substrate comprising a solder mask, a first contact point, a second contact point separate from said first contact point, and an interconnect covered by said solder mask, wherein none of said solder mask is between said first and second contact points; a semiconductor device comprising a polymer layer at a top of said semiconductor device and a metal pad having a third contact point at a bottom of an opening in said polymer layer; a copper pillar between said third contact point and said substrate, wherein said copper pillar is connected to said third contact point through said opening, wherein said copper pillar has a thickness between 10 and 100 micrometers; a solder between said copper pillar and said substrate, wherein said solder is connected to said copper pillar, wherein said solder electrically contacts said first contact point; and an underfill between said semiconductor device and said substrate, wherein said underfill contacts said semiconductor device and said substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill. - View Dependent Claims (19, 20, 21, 22, 23)
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24. A chip package comprising:
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a semiconductor device comprising multiple first contact pads arranged along a first edge of said semiconductor device and in a peripheral region of said semiconductor device, multiple second contact pads arranged along a second edge of said semiconductor device and in said peripheral region, wherein said first edge is opposite to said second edge, multiple third contact pads arranged along a third edge of said semiconductor device and in said peripheral region, and multiple fourth contact pads arranged along a fourth edge of said semiconductor device and in said peripheral region, wherein said third edge is opposite to said fourth edge; a solder mask over said semiconductor device, wherein no solder mask is between any neighboring two of said multiple first contact pads from a top perspective view; a circuit substrate over said semiconductor device; multiple metal bumps between said circuit substrate and said multiple first, second, third and fourth contact pads, wherein one of said multiple metal bumps comprises a copper pillar having a thickness between 10 and 100 micrometers, and a solder between said copper pillar and said circuit substrate, wherein said solder joins said circuit substrate and is connected to said copper pillar; and an underfill between said semiconductor device and said circuit substrate, wherein said underfill contacts said semiconductor device and said circuit substrate, wherein said copper pillar has a sidewall with a bottom edge not covered by said solder, but covered by said underfill. - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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Specification