Method of making 3D integrated circuits

• US 8,158,515 B2
• Filed: 02/01/2010
• Issued: 04/17/2012
• Est. Priority Date: 02/03/2009
• Status: Active Grant

• Current Assignee: Globalfoundries US Incorporated (GlobalFoundries, Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Farooq, Mukta G., Iyer, Subramanian S., Koester, Steven J., Zhu, Huilong
• Primary Examiner(s): NGUYEN, THANH T
• Application Number:
  US12/697,562
• Publication Number:
  US 20100193964A1
• Time in Patent Office: 806 Days
• Field of Search: 438/667, 438637-638, 438/455, 438/459
• US Class Current: 438/667
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/80001 by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/80896 between electrically insulating surfaces, e.g. oxide or nitride layers
• CPC Class Codes: H01L 2224/81894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/821 Forming a build-up interconnect
• CPC Class Codes: H01L 2224/83894 Direct bonding, i.e. joining surfaces by means of intermolecular attracting interactions at their interfaces, e.g. covalent bonds, van der Waals forces
• CPC Class Codes: H01L 2224/9202 Forming additional connectors after the connecting process
• CPC Class Codes: H01L 2224/9212 Sequential connecting processes
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence

Abstract

A method and structure of connecting at least two integrated circuits in a 3D arrangement by a through silicon via which simultaneously connects a connection pad in a first integrated circuit and a connection pad in a second integrated circuit.

Claims

1. A method of making 3D integrated circuits, comprising the steps of:

(a) forming at least one trench in a first semiconductor wafer;

(b) filling the at least one trench with an insulator to form a filled trench;

(c) forming devices and back end of the line (BEOL) wiring on a first side of the first semiconductor wafer with at least one pad in the BEOL wiring aligned with the at least one filled trench;

(d) joining the first semiconductor wafer to a second semiconductor wafer having at least one landing pad aligned with the at least one filled trench in the first semiconductor wafer;

(e) etching the at least one filled trench to remove the insulator;

(f) forming an insulative spacer on the walls of the at least one trench;

(g) continuing etching the at least one trench until the at least one pad and the at least one landing pad are exposed; and

(h) filling the at least one trench with an electrical conductor to simultaneously connect the at least one pad and the at least one landing pad with the electrical conductor.

2. The method of claim 1 further comprising the step after step (b) of etching back the insulator.

3. The method of claim 1 further comprising the step after step (c) of depositing a layer of insulator over the BEOL wiring.

4. The method of claim 1 wherein the second semiconductor wafer has a BEOL wiring and the at least one landing pad is in the BEOL wiring.

5. The method of claim 4 wherein in step (d), the joining is by joining the BEOL wiring of the first semiconductor wafer to the BEOL wiring of the second semiconductor wafer.

6. The method of claim 1 further comprising the steps, between steps (d) and (e) of:

recessing the first semiconductor wafer on a second side so as to expose the at least one filled trench;

depositing a layer of nitride over the second side of the first semiconductor wafer and the exposed at least one filled trench; and

depositing polysilicon over the layer of nitride.

7. The method of claim 1 wherein step (f) comprises depositing an insulator in the trench and then etching out the insulator to leave an insulative spacer on the walls of the at least one trench.

8. The method of claim 1 wherein the trench in step (h) has a center portion, two ends and a width which is narrower in the center portion than in the two ends.

9. A method of making 3D integrated circuits, comprising the steps of:

(a) forming at least one trench in a first semiconductor wafer, the at least one trench extending from a first side of the first semiconductor wafer;

(b) filling the at least one trench with an insulator;

(c) forming devices and back end of the line (BEOL) wiring on the first side of the first semiconductor wafer with at least one pad in the BEOL wiring aligned with the at least one trench, the BEOL wiring having an exposed surface;

(d) obtaining a second semiconductor wafer having BEOL wiring, the BEOL wiring having at least one landing pad and an exposed surface;

(e) joining the exposed surface of the BEOL wiring of the first semiconductor wafer to the exposed surface of the BEOL wiring of the second semiconductor wafer such that the at least one landing pad is aligned with the at least one trench;

(f) etching the first semiconductor wafer from a second side so as to join with the at least one trench and continuing etching of the at least one trench to remove the insulator and stopping in the BEOL wiring;

(g) forming an oxide spacer on the walls of the at least one trench;

(h) continuing etching the at least one trench until the at least one pad and the at least one landing pad are exposed; and

(i) filling the at least one trench with an electrical conductor to simultaneously connect the at least one pad and the at least one landing pad with the electrical conductor.

10. The method of claim 9 further comprising the step after step (b) of etching back the insulator.

11. The method of claim 9 further comprising the step after step (c) of depositing a layer of insulator over the BEOL wiring.

12. The method of claim 9 further comprising the steps, between steps (e) and (f) of:

recessing the first semiconductor wafer on a second side so as to expose the at least one trench;

depositing a layer of nitride over the second side of the first semiconductor wafer and the exposed at least one trench; and

depositing polysilicon over the layer of nitride.

13. The method of claim 9 wherein step (g) comprises depositing an insulator in the trench and then etching out the insulator to leave an insulative spacer on the walls of the at least one trench.

14. The method of claim 9 wherein the trench in step (i) has a center portion, two ends and a width which is narrower in the center portion than in the two ends.