High voltage (>100V) lateral trench power MOSFET with low specific-on-resistance

• US 8,159,024 B2
• Filed: 04/20/2008
• Issued: 04/17/2012
• Est. Priority Date: 04/20/2007
• Status: Active Grant

• Current Assignee: Rensselaer Polytechnic Institute
• Original Assignee: Rensselaer Polytechnic Institute
• Inventors: Chow, Tat-sing Paul, Varadarajan, Kamal Raj
• Primary Examiner(s): PERT, EVAN T
• Application Number:
  US12/596,593
• Publication Number:
  US 20100163988A1
• Time in Patent Office: 1,458 Days
• Field of Search: 257/330, 257/386, 257/409, 257/488, 257/E29.118, 257/E29.257, 257/E21.418, 257/E21.629, 438/268, 438/269, 438/270, 438/273
• US Class Current: 257/330
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/4975 being a silicide layer, e.g. TiSi2
• CPC Class Codes: H01L 29/66704 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7825 with trench gate electrode trench gate electrodes per se H01L29/4236

Abstract

In one aspect, a lateral MOS device is provided. The lateral MOS device includes a gate electrode disposed at least partially in a gate trench to apply a voltage to a channel region, and a drain electrode spaced from the gate electrode, and in electrical communication with a drift region having a boundary with a lower end of the channel region. The device includes a gate dielectric layer in contact with the gate electrode, and disposed between the gate electrode and the drain electrode. The channel region is adjacent to a substantially vertical wall of the gate trench. The device includes a field plate contacting the gate electrode and configured to increase a breakdown voltage of the device.

Claims

1. An apparatus comprising:

a semiconductor substrate;

an epitaxial layer disposed on the semiconductor substrate and configured to provide a drift region;

a body portion contacting the drift region and configured to provide a channel for current flow when a bias signal is applied to a gate electrode;

a source region contacting the body portion;

a gate trench formed in the epitaxial layer;

the gate electrode formed at least partially in the gate trench and extending to a first depth in the gate trench;

a field plate formed at least partially in the gate trench and extending to a second depth, greater than the first depth, in the gate trench; and

a dielectric material comprising a first portion disposed in the gate trench between the gate electrode and the source region and a second portion disposed in the gate trench between the field plate and the epitaxial layer.

2. The apparatus of claim 1, further comprising a drain region contacting the drift region and configured to be in electrical connection with the source region when the bias signal is applied to the gate electrode.

3. The apparatus of claim 2, wherein the drift region is formed in the epitaxial layer so that current flows from the source region to the drain region through the channel region and the drift region when the bias signal is applied to the gate electrode.

4. The apparatus of claim 2, further comprising a spacer region formed in a trench in the epitaxial layer and disposed between the source region and the drain region.

5. The apparatus of claim 4, wherein the spacer region has a depth substantially equal to a depth of the gate trench.

6. The apparatus of claim 4, wherein the spacer region comprises an oxide material.

7. The apparatus of claim 4, wherein the spacer region is substantially surrounded on three sides by the epitaxial layer.

8. The apparatus of claim 1, wherein the gate electrode and the field plate comprise polysilicon.

9. The apparatus of claim 1, wherein the gate electrode contacts the field plate.

10. The apparatus of claim 1, wherein the first portion of the dielectric material in the gate trench has a first thickness, and wherein the second portion of the dielectric material disposed between the field plate and the epitaxial layer has a second thickness greater than the first thickness.

11. A method of manufacturing a lateral trench-based device, comprising:

forming an epitaxial layer on a semiconductor substrate;

forming a gate trench in the epitaxial layer;

filling at least a portion of the gate trench with a dielectric material;

forming a gate electrode in the dielectric material, the gate electrode extending to a first depth in the gate trench; and

forming a field plate in the dielectric material, the field plate extending to a second depth, greater than the first depth, in the gate trench.

12. The method of claim 11, further comprising forming the gate electrode to contact the field plate.

13. The method of claim 11, further comprising forming a source region in the epitaxial layer and a drain region in the epitaxial layer, and forming an oxide spacer region between the source region and the drain region.

14. The method of claim 13, wherein forming the oxide trench comprises forming a trench in the epitaxial layer and filling at least a portion of the trench with an oxide material.