Semiconductor device and method of manufacturing the same

• US 8,159,036 B2
• Filed: 06/18/2008
• Issued: 04/17/2012
• Est. Priority Date: 06/20/2007
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Matsudai, Tomoko, Yasuhara, Norio, Obatake, Manji
• Primary Examiner(s): Richards, N Drew
• Assistant Examiner(s): Lee, Jae
• Application Number:
  US12/141,386
• Publication Number:
  US 20080315305A1
• Time in Patent Office: 1,399 Days
• Field of Search: 257/336, 257/344, 257/408
• US Class Current: 257/408
• CPC Class Codes: H01L 21/2652 Through-implantation
• CPC Class Codes: H01L 21/2658 of a molecular ion, e.g. decaborane
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66659 with asymmetry in the channel direction, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A LDD layer of the second conduction type locates in the surface of a semiconductor layer beneath a sidewall insulator film. A source layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the LDD layer. A resurf layer of the second conduction type is formed in the surface of the semiconductor layer at a position sandwiching the gate electrode with the LDD layer. A drain layer of the second conduction type is formed in the surface of the semiconductor layer at a position adjacent to the resurf layer. The resurf layer is formed in depth to have peaks of a first and a second impurity concentration in turn from the surface of the semiconductor layer. The peak of the first impurity concentration is smaller than the peak of the second impurity concentration.

Claims

1. A semiconductor device, comprising:

a LDMOS transistor, the LDMOS transistor comprising;

a semiconductor layer of a first conduction type;

a gate electrode formed on said semiconductor layer via an insulator layer;

a sidewall insulator film formed on sides of said gate electrode;

an LDD layer of a second conduction type located in the surface of said semiconductor layer beneath said sidewall insulator film;

a source layer of the second conduction type formed in the surface of said semiconductor layer at a position adjacent to said LDD layer;

a resurf layer of the second conduction type formed in the surface of said semiconductor layer at a position sandwiching said gate electrode with said LDD layer, said resurf layer formed under said sidewall insulator film; and

a drain layer of the second conduction type formed in the surface of said semiconductor layer at a position adjacent to said resurf layer,

wherein said resurf layer includes a first resurf layer having a peak of a first impurity concentration and a second resurf layer formed below the first resurf layer and having a peak of a second impurity concentration,

wherein said peak of said first impurity concentration is smaller than said peak of said second impurity concentration, and

the cross-section of the second resurf layer in a plane perpendicular to the surface of said semiconductor layer is larger than that of the first resurf layer in a plane perpendicular to the surface of said semiconductor layer.

2. The semiconductor device according to claim 1, wherein said resurf layer is formed through ion implantation executed multiple times.

3. The semiconductor device according to claim 1, wherein said resurf layer is formed through ion implantation executed multiple times at different acceleration voltages.

4. The semiconductor device according to claim 1, wherein said gate electrode has sides, which are formed oblique such that said gate electrode is tapered downward from above.

5. The semiconductor device according to claim 4, wherein said resurf layer is formed through ion implantation executed multiple times.

6. The semiconductor device according to claim 1, wherein said gate electrode has sides, at least one of which is formed oblique to the surface of said semiconductor layer, wherein said gate electrode has a longer lateral length at the upper surface than at the lower surface.