Programmable integrated circuit with voltage domains

• US 8,159,263 B1
• Filed: 04/29/2010
• Issued: 04/17/2012
• Est. Priority Date: 04/29/2010
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Tuan, Tim, Cline, Ronald L., Rahman, Arifur
• Primary Examiner(s): Tan, Vibol
• Application Number:
  US12/770,559
• Time in Patent Office: 719 Days
• Field of Search: 326/63, 326/68, 326/81, 326/83, 326/86, 326 38- 41, 327/333
• US Class Current: 326/38
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/018585 programmable

Abstract

A programmable integrated circuit having a plurality of individually controlled voltage domains. Each voltage domain includes logic circuitry powered by a respective power network. The voltage magnitude of each power network is independently selectable. Each of a plurality of level shifters couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port. The first signaling protocol is referenced to the voltage magnitude of the first voltage domain, and the second signaling protocol is referenced to the voltage magnitude of the second voltage domain. Means are disclosed for controlling the voltage magnitude of the respective power network of one or more of the voltage domains.

Claims

1. A programmable integrated circuit, comprising:

a plurality of voltage domains each including logic circuitry powered by a respective power network;

wherein a voltage magnitude of the respective power network of each voltage domain is independently selectable for specifying a tradeoff between performance and power consumption of the logic circuitry in the voltage domain;

a plurality of level shifters;

wherein each level shifter couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port, the first signaling protocol referenced to the voltage magnitude of the respective power network powering the logic circuitry of the first voltage domain and the second signaling protocol referenced to the voltage magnitude of the respective power network powering the second voltage domain; and

a control circuit coupled to the logic circuitry in each of the plurality of voltage domains, the control circuit configured and arranged to independently control the voltage magnitude of the respective power network of each of the voltage domains.

2. The programmable integrated circuit of claim 1, wherein the control circuit is further configured and arranged to independently control a voltage bias of a substrate of each of the voltage domains for specifying the tradeoff between performance and power consumption of the logic circuitry in the voltage domain.

3. A programmable integrated circuit, comprising:

a plurality of semiconductor dies including a plurality of respective voltage domains each including logic circuitry powered by a respective power network;

wherein a voltage magnitude of the respective power network of each voltage domain is independently selectable for specifying a tradeoff between performance and power consumption of the logic circuitry in the voltage domain;

a plurality of level shifters;

wherein each level shifter couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port, the first signaling protocol referenced to the voltage magnitude of the respective power network powering the logic circuitry of the first voltage domain and the second signaling protocol referenced to the voltage magnitude of the respective power network powering the second voltage domain; and

a semiconductor interposer coupling the plurality of semiconductor dies, the semiconductor interposer providing a plurality of power ports for independently controlling the voltage magnitude of the respective power network of each voltage domain.

4. The programmable integrated circuit of claim 3, wherein:

the logic circuitry in one of the voltage domains is active during a first time interval and inactive during a second time interval;

the power ports set the voltage magnitude of the respective power network of the voltage domain to an operating voltage magnitude for achieving proper performance of the logic circuitry throughout the first time interval;

the power ports set the voltage magnitude to a standby voltage magnitude within the second time interval; and

the logic circuitry in the voltage domain has a power consumption during the second time interval that is lower than a power consumption of the logic circuitry if the voltage magnitude was instead set to the operating voltage magnitude throughout the second time interval.

5. The programmable integrated circuit of claim 3, wherein:

the logic circuitry in a first one of the voltage domains is critical logic circuitry requiring a first level of performance;

the logic circuitry in a second one of the voltage is non-critical logic circuitry requiring a second level of performance that is lower than the first level of performance;

the power ports set the voltage magnitude of the respective power network of the first voltage domain to a first voltage magnitude for achieving the first level of performance of the critical logic circuitry; and

the power ports set the voltage magnitude of the respective power network of the second voltage domain to a second voltage magnitude for achieving the second level of performance at a power consumption of the non-critical logic circuitry that is lower than a power consumption of the non-critical logic circuitry if the voltage magnitude for the second voltage domain was instead set to the first voltage magnitude.

6. The programmable integrated circuit of claim 3, wherein:

the semiconductor die for each voltage domain includes a generator of a voltage bias of a substrate of the semiconductor die; and

the generator controls the voltage bias of the substrate for specifying a tradeoff between performance and power consumption of the logic circuitry in the voltage domain.

7. The programmable integrated circuit of claim 6, wherein:

the logic circuitry in one of the voltage domains is active during a first time interval and inactive during a second time interval;

the generator sets the voltage bias of the substrate of the semiconductor die of the voltage domain to an operating bias for achieving proper performance of the logic circuitry throughout the first time interval;

the generator sets the voltage bias to a standby bias within the second time interval; and

the logic circuitry in the voltage domain has a power consumption during the second time interval that is lower than a power consumption of the logic circuitry if the voltage bias was instead set to the operating bias throughout the second time interval.

8. The programmable integrated circuit of claim 6, wherein:

the logic circuitry in a first one of the voltage domains is critical logic circuitry requiring a first level of performance and the logic circuitry in a second one of the voltage is non-critical logic circuitry requiring a second level of performance that is lower than the first level of performance;

the generator in the first voltage domain sets the voltage bias of the substrate of the semiconductor die of the first voltage domain to a first operating bias for achieving the first level of performance of the critical logic circuitry; and

the generator in the second voltage domain sets the voltage bias of the substrate of the semiconductor die of the second voltage domain to a second operating bias for achieving the second level of performance at a power consumption of the non-critical logic circuitry that is lower than a power consumption of the non-critical logic circuitry if the voltage bias for the second voltage domain was instead set to the first operating bias.

9. The programmable integrated circuit of claim 3, wherein, for each of the level shifters, the semiconductor interposer couples the first port of the logic circuitry in the semiconductor die of the first voltage domain via the level shifter to the second port of the logic circuitry in the semiconductor die of the second voltage domain.

10. The programmable integrated circuit of claim 9, wherein, for two of the semiconductor dies providing the first and second voltage domains for each level shifter, the level shifter is provided by at least one of the two semiconductor dies.

11. A programmable integrated circuit, comprising:

a plurality of voltage domains each including logic circuitry powered by a respective power network;

wherein a voltage magnitude of the respective power network of each voltage domain is independently selectable for specifying a tradeoff between performance and power consumption of the logic circuitry in the voltage domain;

a plurality of level shifters;

wherein each level shifter couples a first and second one of the voltage domains, couples a first port of the logic circuitry of the first voltage domain to a second port of the logic circuitry of the second voltage domain, and shifts from a first signaling protocol of the first port to a second signaling protocol of the second port, the first signaling protocol referenced to the voltage magnitude of the respective power network powering the logic circuitry of the first voltage domain and the second signaling protocol referenced to the voltage magnitude of the respective power network powering the second voltage domain;

a configuration device specifying at least one power state for the voltage domains, each power state independently selected from a plurality of power states including at least a powered state and a non-powered state; and

a selector coupled to at least one of the voltage domains and the configuration device;

wherein, for each voltage domain that is coupled to the selector, the selector selects the voltage magnitude corresponding to the at least one power state to the respective power network of the voltage domain.

12. The programmable integrated circuit of claim 11, wherein:

the logic circuitry in the voltage domains includes a plurality of programmable logic and interconnect resources; and

each level shifter couples the first port of the programmable logic resources in the first voltage domain via the programmable interconnect resources to the second port of the programmable logic resources in the second voltage domain.

13. The programmable integrated circuit of claim 12, wherein:

each level shifter includes a half-latch powered by the respective power network of the second voltage domain, the half-latch including an inverter and a PMOS pull-up transistor;

the first port is coupled via at least one pass transistor of the programmable interconnect resources to an input of the inverter;

an output of the inverter is coupled to the second port and a gate of the PMOS pull-up transistor; and

a channel electrode of the PMOS pull-up transistor is coupled to the input of the inverter.

14. The programmable integrated circuit of claim 13, wherein:

the at least one pass transistor electrically decouples the respective power networks of the first and second voltage domains, causing the inverter and the PMOS pull-up transistor to drive the input of the inverter to the voltage magnitude of the respective power network of the second voltage domain, in response to the first node driving the voltage magnitude of the respective power network of the first voltage domain and in response to a gate voltage magnitude of the at least one pass transistor being less than a sum of a threshold voltage magnitude of the at least one pass transistor and the voltage magnitude of the respective power network of the first voltage domain.

15. The programmable integrated circuit of claim 11, wherein:

in the powered state for the voltage domain, the selector sets the voltage magnitude of the respective power network of the voltage domain to an operating voltage magnitude for achieving proper performance of the logic circuitry in the voltage domain; and

in the unpowered state for the voltage domain, the selector sets the voltage magnitude of the respective power network of the voltage domain to a grounded voltage magnitude for eliminating power consumption of the logic circuitry in the voltage domain.

16. The programmable integrated circuit of claim 15, wherein:

the configuration device includes a fuse device having an electrically alterable resistance; and

for each voltage domain that is coupled to the selector, the fuse device selects the powered state in response to the electrically alterable resistance being less than a threshold resistance and the fuse device selects the unpowered state in response to the electrically alterable resistance being more than the threshold resistance.

17. The programmable integrated circuit of claim 16, wherein the fuse device is configured to select the unpowered state in response to the voltage domains that are coupled to the selector having a fabrication defect that precludes proper performance of the logic circuitry in these voltage domains.

18. The programmable integrated circuit of claim 15, wherein:

the configuration device includes a predetermined one of a plurality of available interposers;

a first one of the available interposers selects the powered state for each of the voltage domains; and

a second one of the available interposers selects the unpowered state for each of at least one of the voltage domains.

19. The programmable integrated circuit of claim 15, wherein, for each level shifter that couples the first port of the first voltage domain to the second port of the second voltage domain, the level shifter includes an isolation circuit that disables the first port in response to the first voltage domain having the unpowered state.

20. The programmable integrated circuit of claim 11, wherein:

each of the voltage domains is disposed within at least one isolation well of a semiconductor of the programmable integrated circuit;

associated with each of the voltage domains is a generator of a voltage bias for the at least one isolation well of the voltage domain; and

the generator controls the voltage bias of the at least one isolation well of the voltage domain for specifying a tradeoff between performance and power consumption of the logic circuitry in the voltage domain.