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Memory for metal configurable integrated circuits

  • US 8,159,265 B1
  • Filed: 11/16/2010
  • Issued: 04/17/2012
  • Est. Priority Date: 11/16/2010
  • Status: Expired due to Fees
First Claim
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1. A memory array of a semiconductor device, comprising:

  • a memory cell replicated in rows and columns to form an array; and

    a plurality of first horizontal decode signals, each horizontal signal common to all the memory cells in a said row; and

    a plurality of first vertical decode signals, each vertical signal common to all the memory cells in said column;

    wherein, said replicated memory cell further comprises;

    a storage device to store data; and

    a first decode device to receive said first horizontal decode signal and said first vertical decode signal and generate a first local decode signal to access a first unique memory cell in the array; and

    a first select device coupled to the storage device and the first decode device, wherein the first local decode signal provides access to the first unique cell in the array from the plurality of first horizontal and first vertical decode signals.

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