Metal configurable integrated circuits
First Claim
1. A semiconductor device, comprising:
- a metal programmable logic circuit; and
a plurality of fixed interconnect geometries including metal and via structures; and
a plurality of selectable interconnect geometries, each said selectable interconnect geometry capable of coupling a first of said fixed interconnects to a second of said fixed interconnects; and
a binary bitstream, each bit in the bitstream assigned to one or more of said selectable interconnect geometries, wherein the binary state of said bit specifies if said assigned one or more selectable Interconnect geometries is included or excluded in the selection; and
a computer aided design tool that identifies one or more logic functions and an interconnect pattern to fully program the metal programmable logic circuit to a user specification by identifying the bit states of said binary bitstream; and
at least one custom mask comprising a portion of said fixed interconnect geometries and a portion of the bitstream selected geometries of said one or more selectable interconnect geometries, wherein the said at least one custom mask programs the metal programmable logic circuit to the customer specification during fabrication of the semiconductor device.
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Abstract
A metal programmable semiconductor device is disclosed. The semiconductor device, comprises: a metal programmable logic circuit; and a plurality of fixed interconnect geometries including metal and via structures; and a plurality of selectable interconnect geometries, each said interconnect geometry capable of coupling a first of said fixed interconnects to a second of said fixed interconnects; and a binary bitstream, each bit in the bitstream assigned to one or more of said selectable interconnect geometries, wherein the binary state of a said bit specifies if said assigned one or more selectable geometries is included or excluded in the selection; and a computer aided design tool that identifies one or more logic functions and an interconnect pattern to fully program the logic circuit to a user specification by identifying the bit states of said binary bitstream; and at least one custom mask comprising a portion of said fixed interconnect geometries and a portion of the bitstream selected geometries of said one or more selectable interconnect geometries, wherein the said at least one custom mask programs the programmable circuit to the customer specification during fabrication of the semiconductor device.
101 Citations
20 Claims
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1. A semiconductor device, comprising:
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a metal programmable logic circuit; and a plurality of fixed interconnect geometries including metal and via structures; and a plurality of selectable interconnect geometries, each said selectable interconnect geometry capable of coupling a first of said fixed interconnects to a second of said fixed interconnects; and a binary bitstream, each bit in the bitstream assigned to one or more of said selectable interconnect geometries, wherein the binary state of said bit specifies if said assigned one or more selectable Interconnect geometries is included or excluded in the selection; and a computer aided design tool that identifies one or more logic functions and an interconnect pattern to fully program the metal programmable logic circuit to a user specification by identifying the bit states of said binary bitstream; and at least one custom mask comprising a portion of said fixed interconnect geometries and a portion of the bitstream selected geometries of said one or more selectable interconnect geometries, wherein the said at least one custom mask programs the metal programmable logic circuit to the customer specification during fabrication of the semiconductor device. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A user configurable semiconductor device, comprising:
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a computer aided design tool that identifies a binary bitstream to implement a design to a user specification, the binary states comprising one and zero; and at least one interconnect layer comprising a plurality of fixed interconnect geometries and a plurality of selectable interconnect geometries, wherein a subset of the selectable geometries are selected by the state of one or more bits in said bitstream; and at least one custom mask comprising the plurality of fixed interconnect geometries and the subset of selectable interconnect geometries selected by the bitstream; and a plurality of common masks comprising a plurality of fixed geometries that are invariant of said user specification; and a fabrication process to fabricate the device, the process utilizing said plurality of common masks and said at least one custom mask, wherein said at least one custom mask programs the semiconductor device to the user specification. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A mask configurable semiconductor device, comprising:
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a plurality of mask configurable logic structures; and a plurality of mask configurable interconnects; and a plurality of fixed geometries, the fixed geometries including a plurality of fixed interconnect geometries; and a plurality of selectable interconnect geometries; and at least one custom mask comprising said plurality of fixed interconnect geometries, and a subset of said plurality of selectable interconnect geometries, wherein the customization is achieved by selecting the subset of selectable interconnect geometries to be included in the custom mask; and a plurality of common masks, each of said common masks comprising a subset of the plurality of fixed geometries; and a fabrication process to fabricate the device, the process utilizing said plurality of common masks and said at least one custom mask, wherein said at least one custom mask programs said mask configurable logic and interconnects to a user specification. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification