Interconnect structures for metal configurable integrated circuits

• US 8,159,268 B1
• Filed: 11/16/2010
• Issued: 04/17/2012
• Est. Priority Date: 11/16/2010
• Status: Expired due to Fees

• Current Assignee: Raminda Udaya Madurawe
• Original Assignee: Raminda Udaya Madurawe
• Inventors: Madurawe, Raminda Udaya
• Primary Examiner(s): Ismail, Shawki S
• Assistant Examiner(s): TRAN, THIENVU V
• Application Number:
  US12/947,606
• Time in Patent Office: 518 Days
• Field of Search: 326 37- 41, 326/47, 326/101
• US Class Current: 326/47
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/11807 CMOS gate arrays

Abstract

Interconnect structure comprising buffers for a semiconductor device is disclosed. The buffer comprises: an input and an output; and a programmable interconnect structure comprising: a plurality of fixed interconnects including metal and via geometries; and a plurality of selectable interconnect geometries, wherein selecting a selectable geometry connects a first of said fixed interconnects to a second of said fixed interconnects; wherein said input and said output can electrically connect to a subset of said fixed interconnects by the selectable geometries; and a programmable signal restoring unit comprising a plurality of transistors, at least one said transistor having: a common gate region and a common source region; and a first drain region coupled to the buffer output comprising a said fixed interconnect; and a second drain region comprising a said fixed interconnect, said first and second drain regions isolated from each other, wherein a said selectable interconnect geometry can electrically connect the first and second drain regions; wherein, selecting a subset of the selectable interconnect geometries program the buffer input and output connections, and the buffer signal drive strength.

Claims

1. A programmable buffer of a semiconductor device comprising:

an input and an output; and

a programmable interconnect structure comprising;

a plurality of fixed interconnects including metal and via geometries; and

a plurality of selectable interconnect geometries, wherein selecting a selectable geometry connects a first of said fixed interconnects to a second of said fixed interconnects;

wherein said input and said output is configured to electrically connect to a subset of said fixed interconnects by the selectable interconnect geometries; and

a programmable signal restoring unit comprising a plurality of transistors, at least one said transistor having;

a common gate region and a common source region; and

a first drain region coupled to the programmable buffer output comprising said fixed interconnect; and

a second drain region comprising said fixed interconnect, said first and second drain regions isolated from each other, wherein said selectable geometry is configured to electrically connect the first and second drain regions;

wherein, selecting a subset of the selectable interconnect geometries program the programmable buffer input and output connections, and the programmable buffer signal drive strength.

2. The device of claim 1, wherein said at least one transistor is one of an NMOS transistor and a PMOS transistor.

3. The device of claim 1, wherein said selectable interconnect geometry is one of a via geometry and a metal geometry.

4. The device of claim 1, wherein the selectable interconnect geometries further require a custom interconnect layer to fabricate the buffer, the custom interconnect layer comprising:

a portion of said fixed interconnect geometries; and

the subset of said selectable interconnect geometries, said subset selected by a computer aided design tool by the use of a binary bit of said binary bitstream, said binary bit comprising a one state to select the selectable geometry and a zero state to omit the selectable geometry;

wherein the custom interconnect layer program the programmable buffer during fabrication of the semiconductor device.

5. The device of claim 1, further comprising:

a first configuration wherein the programmable buffer comprises a first signal drive strength; and

a second configuration wherein the programmable buffer comprises a second signal drive strength greater than said first drive strength.

6. The device of claim 1, wherein the fixed interconnect geometries further require at least one interconnect layer to fabricate the programmable buffer wherein there are no selectable interconnect geometries.

7. The device of claim 1, wherein said signal restoring unit further comprising:

a first inverter having an input and an output, wherein the programmable buffer input is coupled to the first inverter input; and

a second inverter having an input and an output, wherein the first inverter output is coupled to the second inverter input, and the second inverter output is coupled to the programmable buffer output.

8. The device of claim 1, wherein said at least one transistor of the restoring unit further comprising:

an N^th isolated drain region, where N is an integer greater than two, the N^th drain region coupled to a said fixed interconnect, wherein said first, second and N^th drain regions is configured to electrically connect to each other by selecting a subset of said selectable geometries.

9. A programmable buffer of a semiconductor device, comprising:

a plurality of fixed interconnect geometries and a plurality of selectable interconnect geometries, wherein selecting a selectable geometry connects a first of said fixed interconnects to a second of said fixed interconnects; and

a programmable buffer comprising;

an input and an output, the input and the output capable of connecting to a subset of said fixed interconnects by a subset of said selectable interconnect geometries; and

a plurality of inverters coupled to the programmable buffer input and the programmable buffer output, a first of said inverter comprising a first transistor comprised of a plurality of isolated drain nodes, wherein the drain nodes is configured to be connected to each other by selecting a subset of said selectable interconnect geometries; and

a computer aided design tool that identifies a binary bitstream, a binary bit of said binary bitstream having a one state to select the selectable geometry, and a zero state to omit the selectable geometry, the bitstream identifying the selectable geometries to program the programmable buffer input and output connections, and the programmable buffer drive strength; and

a fabrication process utilizing a plurality of common interconnect layers and a custom interconnect layer to fabricate the device, the custom interconnect layer comprising a subset of said fixed interconnect geometries and the bitstream selected selectable interconnect geometries to program the programmable buffer.

10. The device of claim 9, wherein said first transistor is one of an NMOS transistor and a PMOS transistor.

11. The device of claim 9, wherein said custom interconnect layer comprises one of a via layer and a metal layer.

12. The device of claim 9, further comprising:

a first bitstream to insert the programmable buffer having a first strength between a first and second of said fixed interconnects; and

a second bitstream to insert the programmable buffer having a second strength between a third and fourth of said fixed interconnects.

13. The device of claim 9, wherein said first transistor further comprises:

a common gate node receiving an input signal, a common source node providing a fixed source voltage, wherein a first portion of the transistor on current is supplied to the first drain, and wherein a second portion of the transistor on current is supplied to the second drain.

14. The device of claim 9, wherein the first inverter further comprises:

a second transistor comprised of a plurality of isolated drain nodes, wherein the drain nodes are configured to be connected to each other by selecting a subset of said selectable interconnect geometries, and wherein said first and second transistors have opposite channel conductivity.

15. A programmable interconnect structure of a semiconductor device, comprising:

a plurality of programmable interconnects comprising;

a plurality of fixed interconnects including metal and via geometries; and

a plurality of selectable interconnect geometries, wherein selecting a selectable geometry connects a first said fixed interconnects to a second said fixed interconnects; and

a plurality of programmable buffers, each programmable buffer comprising;

an input, wherein selecting a subset of said selectable interconnect geometries connect the input to one of a subset of said fixed interconnects; and

an output, wherein selecting a subset of said selectable interconnect geometries connect the output to one of a subset of said fixed interconnects; and

a plurality of inverters, a first of said inverters having a first transistor comprised of;

a first drain region coupled to the programmable buffer output; and

a second drain region isolated from said first drain region, wherein selecting said selectable geometry connects the second drain region to the first drain region to increase the drive strength of the programmable buffer;

wherein, selecting a subset of the selectable interconnect geometries program the programmable interconnect structure to a customer specification.

16. The device of claim 15, wherein said first transistor is one of an NMOS transistor and a PMOS transistor.

17. The device of claim 15, wherein said selectable geometry is one of a via geometry and a metal geometry.

18. The device of claim 15, wherein the selectable interconnect geometries further require a custom interconnect layer to fabricate the interconnect structure, the custom interconnect layer comprising:

a portion of said fixed interconnect geometries; and

a subset of selectable interconnect geometries, said subset selected by a computer aided design tool by the use of a binary bitstream, a binary bit of said binary bitstream comprising a one state to select the selectable geometry and a zero state to omit the selectable geometry;

wherein the custom interconnect layer program the interconnect structure during fabrication of the semiconductor device.

19. The device of claim 15, further comprising:

a first instance wherein a single buffer having a first strength is positioned between a first and second of said fixed interconnects; and

a second instance wherein a plurality of buffer having a second strength is positioned between a third and fourth of said fixed interconnects.

20. The device of claim 15, wherein the first inverter of each buffer further comprises:

a second transistor comprised of a plurality of isolated drain nodes, wherein the first and second transistor drain nodes are configured to be connected to each other by selecting a subset of said selectable interconnect geometries, and wherein said first and second transistors have opposite channel conductivity.