Method of detecting faults using graduated fault detection levels

• US 8,159,362 B2
• Filed: 09/08/2006
• Issued: 04/17/2012
• Est. Priority Date: 10/18/2005
• Status: Active Grant

• Current Assignee: Schweitzer Engineering Laboratories, Incorporated
• Original Assignee: Schweitzer Engineering Laboratories, Incorporated
• Inventors: Swartzendruber, Ryan W., Feight, Laurence Virgil, Salewske, Tyson J.
• Primary Examiner(s): Lee, Benjamin C
• Assistant Examiner(s): TANG, SIGMUND N
• Application Number:
  US11/518,334
• Publication Number:
  US 20070086135A1
• Time in Patent Office: 2,048 Days
• Field of Search: 340/648, 340/664, 361/93, 361/41, 361 42- 50
• US Class Current: 340/648
• CPC Class Codes: H02H 3/04 with warning or supervision in addition to disconnection, e.g. for indicating that protective apparatus has functioned watching of pilot wires H02H1/0084; protection of protective arrangements H02H7/008; indication of the state of electronic switches H03K17/18

Abstract

A faulted circuit indicator utilizes digitized fault indication curves to determine if a fault has occurred in a monitored conductor. Fault indication curves are intended to be similar to trip curves of common power protection devices, and consist of a plurality of associated fault current levels and fault times. The faulted circuit indicator only displays a fault when the current within the monitored conductor exceeds one of the fault current levels for its associated fault time. This results in more accurate fault detection through the ability to distinguish between small and large amplitude faults coupled with the flexability of a fault indicator suitable for use on many different power systems.

Claims

1. A faulted circuit indicator comprising:

i) a housing;

ii) a current acquisition circuit disposed within the housing, the current acquisition circuit adapted to monitor current within a conductor;

iii) an adjustable trip circuit coupled to the current acquisition circuit and producing a trip output when the monitored current exceeds a trip level;

iv) a persistent memory component disposed within the housing, the persistent memory component storing a fault indication curve comprising a plurality of associated fault current levels and fault times, wherein each fault current level is a current level which when exceeded by the monitored current for the duration of the associated fault time, indicates a current fault; and

v) a processor disposed within the housing and coupled to the adjustable trip circuit and the persistent memory component, the processor adjusting a the trip level of the adjustable trip circuit after a time period has elapsed and based on the fault indication curve and producing a fault signal based on the trip output and the fault indication curve.

2. The faulted circuit indicator of claim 1, wherein the persistent memory component is contained within the processor.

3. The faulted circuit indicator of claim 1, wherein the processor also determines an average current level within the conductor, and selects an appropriate fault indication curve based on the average current level.

4. The faulted circuit indicator of claim 1, further comprising an averaging circuit disposed within the housing and coupled to the current acquisition circuit and the processor, and wherein the averaging circuit produces an output proportional to the average current level within the conductor, and wherein the processor selects an appropriate fault indication curve based on the output of the averaging circuit.

5. The faulted circuit indicator of claim 1, further comprising a display disposed within the housing and coupled to the processor, and wherein the processor activates the display if a fault has occurred.

6. The faulted circuit indicator of claim 1, wherein the associated fault time is a multiple of power system cycles.

7. The faulted circuit indicator of claim 1, wherein the adjustable trip circuit comprises a digital to analog converter and a comparator.

8. The faulted circuit indicator of claim 1, wherein the adjustable trip circuit is implemented as executable instructions within the processor.

12. The faulted circuit indicator of claim 1, further comprising a display in communication with the housing, and wherein the processor activates the display if a fault has occurred.

13. The faulted circuit indicator of claim 12, wherein the display is remote from the housing.

14. The faulted circuit indicator of claim 1, wherein the processor adjusts the trip level to of the adjustable trip circuit such that the trip level comprises a fault time shorter than a previous fault time for a fault current level that is higher than a previous fault current level.

15. The faulted circuit indicator of claim 1, wherein the time period is a predetermined time period.

9. A method operating within a processor for determining whether a fault has occurred within a monitored conductor, the method comprising the steps of:

i) receiving a level of current within the monitored conductor, resulting in received current;

ii) comparing the received current to a fault indication curve, wherein the fault indication curve comprises a plurality of associated fault current levels and fault times; and

iii) outputting a fault signal if the received current exceeds any particular fault current level of the fault indication curve for the duration of the fault time associated with the particular fault current level.

10. The method of claim 9, further comprising the steps of:

i) calculating an average current level within a monitored conductor for a predetermined period of time from the received current; and

ii) selecting an appropriate fault indication curve based on the average current level.

11. The method of claim 9, wherein the fault time associated with the particular fault current level is a multiple of a power system frequency.