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Hardware implemented pixel level digital filter and processing of electromagnetic signals

  • US 8,159,568 B2
  • Filed: 02/01/2010
  • Issued: 04/17/2012
  • Est. Priority Date: 03/26/2009
  • Status: Expired due to Fees
First Claim
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1. An apparatus for performing digital video calibration of electromagnetic waves for system impurity calibration;

  • a sequence of raster input pixel signals, each respective raster input pixel having, an n-tuple set of values of electromagnetic waves from a video camera or sensors to signify n-tuple intensity identification relating to a pixel, the n-tuple (hereafter called channels) set, that is selected from adjacent or separate bands or sub-bands representing a channel of electromagnetic wave;

    wherein data intensities constituting a set of addresses input to plurality of “

    n”

    memories;

    each memory address pre-loaded with a set of data to represent scaling, calibration, and/or correction, for correcting system caused imperfections, including and not limited to variations in FPA temperature, optical imperfections and or individual pixel impurities affecting sensor data;

    correction made by altering the received sensor data with a pre-recorded or empirically derived data;

    corrections to be made with a cascading memories in which each stage of the memory in the cascading (series) of stages, correcting data due to a different sources of the imperfection shown in FIGS. 2, 2B, and 2C as follows;

    a) a controller for sequencing activity of each stage and to direct the output from any previous stage to the next stage;

    radiometric pixel by pixel corrections for the imperfections of equipment are corrected by setting the CCD frame address such as rows and columns to plurality of Radiometric Correction Memory address generator, wherein the data contents are set to address to the Radiometric Data Correction (substitution), in which the data correction for each pixel is already pre-loaded;

    Memory identify each pixel and data corrections;

    b) inhibit (prevent) corrections along any one of the cascading stages;

    c) the sequence timing to be done with a fastest system clock synchronized to pixel timing or sequencing without timing in which the final (data) settlement of each stage and all the stages, is valid upon electronic propagation settlement of stages;

    d) controller having individual control lines for each stage to transfer data from any previous stage to this stage;

    e) initial stages are allocated to the system imperfections affecting all pixels, and secondary stages will be pixel location related;

    f) each stage consisting of a correction memory in which data contents is the correction a pixel sensor and the address to the memory is sensor data, previous stage sensor data, quantized source of imperfection for each stage or pixel coordinates;

    each correcting memories data preloaded with a set of data to replace the affected sensor data according to FIGS. 2, 2B and 2C;

    g) each stage is armed with correct no correct signal from the controller with additional signal to enable or disable outputs from registers or memories;

    h) controller initially receiving control information from the main CPU or dynamically receiving changes based upon the health of the system.

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