Fabrication of a high fill ratio silicon spatial light modulator

• US 8,159,740 B2
• Filed: 01/20/2010
• Issued: 04/17/2012
• Est. Priority Date: 10/28/2005
• Status: Active Grant

• Current Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Original Assignee: Miradia Inc. (Walsin Lihwa Corporation)
• Inventors: Yang, Xiao, Wang, Yuxiang, Ji, Wook, Payne, Justin Allen, Wang, Ye, Woo, Howard
• Primary Examiner(s): Mack, Ricky
• Assistant Examiner(s): THOMAS, BRANDI N
• Application Number:
  US12/690,878
• Publication Number:
  US 20100112492A1
• Time in Patent Office: 818 Days
• Field of Search: 359/285, 359290-299
• US Class Current: 359/290
• CPC Class Codes: G02B 26/0841 the reflecting element being moved or deformed by electrostatic means

Abstract

A method for forming an optical deflection device includes providing a semiconductor substrate comprising an upper surface region and a plurality of drive devices within one or more portions of the semiconductor substrate. The upper surface region includes one or more patterned structure regions and at least one open region to expose a portion of the upper surface region to form a resulting surface region. The method also includes forming a planarizing material overlying the resulting surface region to fill the at least one open region and cause formation of an upper planarized layer using the fill material. The method further includes forming a thickness of silicon material at a temperature of less than 300° C. to maintain a state of the planarizing material.

Claims

1. A method of fabricating an optical deflection device, the method comprising:

providing a substrate comprising a plurality of electrode devices and a bias grid;

forming a planarized dielectric layer over the substrate;

forming a cavity in the planarized dielectric layer;

performing a layer transfer process to bond a single crystal silicon layer to the planarized dielectric layer;

forming a plurality of vias passing through the single crystal silicon layer and the planarized dielectric layer to the bias grid;

forming a plurality of electrical connections passing through the plurality of vias;

forming a hinge coupled to the substrate;

forming a planarized material layer coupled to the hinge;

forming a cavity in the planarized material layer;

forming a mirror structure filling at least a portion of the cavity; and

releasing the mirror structure.

2. The method of claim 1 further comprising forming a mirror coating layer coupled to the mirror structure.

3. The method of claim 1 wherein the mirror structure comprises:

a mirror post; and

a mirror plate coupled to the mirror post and overlying the substrate.

4. The method of claim 1 wherein the mirror structure comprises a silicon mirror structure.

5. The method of claim 1 wherein the substrate comprises a number of electrodes and associated electrode drivers.

6. The method of claim 1 wherein forming a planarized dielectric layer comprises:

depositing an oxide layer using an HDP process; and

planarizing the deposited oxide layer using a CMP process.

7. The method of claim 6 wherein depositing an oxide layer is performed at a temperature less than a temperature associated with a state change of an underlying material.

8. The method of claim 7 wherein the temperature is less than an aluminum reflow temperature.

9. The method of claim 8 wherein the aluminum reflow temperature is about 450°

C.

10. The method of claim 7 wherein depositing an oxide layer is performed at a temperature less than a glass transition temperature of photoresist.

11. The method of claim 10 wherein the glass transition temperature of photoresist is about 150°

C.

12. The method of claim 1 wherein the layer transfer process comprises a substrate bonding process.

13. The method of claim 12 wherein the substrate bonding process provides a covalent bond between the planarized dielectric layer and the single crystal silicon layer.

14. The method of claim 1 wherein the plurality of vias comprises:

a first set of vias providing an electrical conduction path to a bias line; and

a second set of vias providing an electrical conduction path to a bias grid.

15. The method of claim 1 wherein the plurality of electrical connections comprise via plugs.

16. The method of claim 1 wherein the plurality of electrical connections comprise a conformal metal layer.

17. The method of claim 16 wherein the conformal metal layer comprises a composite Ti/Al layer.

18. The method of claim 1 further comprising forming an upper electrode by patterning and removing a portion of the single crystal silicon layer.

19. The method of claim 1 wherein forming the mirror structure comprises depositing and planarizing an amorphous silicon layer.

20. The method of claim 19 wherein depositing and planarizing an amorphous silicon layer is performed at a temperature of less than 150°

C.

21. The method of claim 1 wherein the mirror structure comprises a polysilicon layer.

22. The method of claim 1 wherein the mirror structure comprises a silicon/metal alloy.

23. The method of claim 22 wherein silicon/metal alloy comprises a silicon/Al alloy.

24. The method of claim 1 wherein the mirror coating layer comprises a composite Ti/Al layer.

25. The method of claim 1 wherein releasing the mirror structure comprises removing the material layer using an O₂ plasma ashing process.

26. The method of claim 1 further comprising fabricating a mirror electrode on a surface of the silicon mirror layer.

27. The method of claim 26 wherein the surface of the silicon mirror layer is a bottom surface opposing the first substrate.

28. The method of claim 1 further comprising:

forming a second plurality of vias, each of the second plurality of vias passing through the single crystal silicon layer and the planarized dielectric layer to one of the plurality of electrode devices; and

forming a second plurality of via plugs, each of the second plurality of via plugs passing through one of the second plurality of vias.

29. The method of claim 28 wherein the second plurality of via plugs provide electrical connectivity to the plurality of electrode devices.