Phase change memory devices and systems, and related programming methods

• US 8,159,867 B2
• Filed: 03/02/2009
• Issued: 04/17/2012
• Est. Priority Date: 04/06/2006
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Cho, Woo-Yeong, Lee, Kwang-Jin, Kim, Hye-Jin
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US12/395,999
• Publication Number:
  US 20090161421A1
• Time in Patent Office: 1,142 Days
• Field of Search: 365/163, 365/148, 365/113, 365/100, 365/189.11
• US Class Current: 365/163
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0076 Write operation performed depending on read result
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A phase change memory device performs a program operation by receiving program data to be programmed in selected memory cells, sensing read data already stored in the selected memory cells by detecting respective magnitudes of verify currents flowing through the selected memory cells when a verify read voltage is applied to the selected memory cells, determining whether the read data is identical to the program data, and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, programming the one or more selected memory cells with the program data.

Claims

1. A method of performing a program operation in a resistance-variable memory device comprising a plurality of resistance-variable memory cells, the method comprising:

supplying at least one pulse current to a selected resistance-variable memory cell;

sensing data stored in the selected resistance-variable memory cell by detecting an amount of a verify current flowing through the selected resistance-variable memory cell;

determining whether the sensed data is identical to data to be programmed in the selected resistance-variable memory cell; and

if the sensed data is determined not to be identical to the data to be programmed, supplying a pulse current to the selected resistance-variable memory cell, a resistance value of the selected resistance-variable memory cell being changed by heat corresponding to the pulse current and the pulse current being increased when the supplying is repeated.

2. The method of claim 1, wherein the selected resistance-variable memory cell stores 1-bit data indicating either one of a RESET state and a SET state.

3. The method of claim 1, wherein the selected resistance-variable memory cell stores multi-bit data indicating one selected from a group of a SET state and a plurality of RESET states.

4. The method of claim 3, wherein the plurality of RESET states comprises a full RESET state and at least one intermediate RESET state defined between the full RESET state and the SET state.

5. The method of claim 4, wherein the at least one intermediate RESET state is defined between the full RESET state and the SET state to ensure a maximum read margin between respective ones of the plurality of RESET states and the SET state.

6. The method of claim 4, wherein the program operation comprises a multi-bit memory cell program operation and each one of the SET state and the plurality of RESET states is characterized by one resistance distribution selected from a plurality of resistance distributions.

7. The method of claim 1, wherein if the sensed data is determined to be identical to the data to be programmed, ending the program operation without further supplying the pulse current to the selected resistance-variable memory cell.

8. The method of claim 1, further comprising:

repeatedly performing the sensing, the determining, and the supplying until the data to be programmed for the selected resistance-variable memory cell is identical to the sensed data.

9. The method of claim 8, wherein sensing of data stored in the selected resistance-variable memory cell comprises performing a read verify operation using an applied read verify voltage following each supplying of the pulse current to the selected resistance-variable memory cell.

10. The method of claim 1, wherein the sensing, the determining, and the supplying ensure adequate control of a resistance value of the selected resistance-variable memory cell, and the pulse current speeds up the Joule effect directly to the point where its efficiency is maximum.

11. The method of claim 1, wherein as the supplying of the pulse current is repeated, an amplitude of the pulse current is gradually increased.

12. The method of claim 11, wherein as the supplying of the pulse current is repeated, the amplitude of the pulse current is gradually increased in an up staircase pattern.

13. The method of claim 1, wherein each one of the plurality of resistance-variable memory cells comprises a resistance-variable material exhibiting a SET state wherein amorphous nuclei of defined number and defined size range are formed, and at least one RESET state wherein amorphous nuclei are formed with at least one of a number greater than the defined number and a size range greater than the defined size range are formed.

14. The method of claim 1, wherein the pulse current is repeatedly supplied to the selected resistance-variable memory cell over a sequence of time periods as a sequence of box-shaped program pulses.

15. The method of claim 1, further comprising:

before supplying the at least one pulse current, initially conditioning the selected resistance-variable memory cell by applying at least one of a full SET current pulse and a RESET current pulse.

16. The method of claim 15, wherein before supplying the at least one pulse current, initially conditioning the selected resistance-variable memory cell by applying the RESET current pulse.

17. The method of claim 16, wherein the data to be programmed corresponds to the RESET state, and upon determining that the sensed data corresponds to the RESET state, ending the program operation without further supplying the pulse current to minimize a programming loop duration for the program operation.

18. A memory device comprising:

a memory array comprising a selected resistance-variable memory cell configured to store program data; and

a generator configured to generate a level-controlled program current and mirror the level-controlled program current throughout the memory array to iteratively apply the level-controlled program current to the selected resistance-variable memory cell,

wherein the level-controlled program current is gradually increased with each iterative application of the level-controlled program current until a programmed state for the selected resistance-variable memory cell is equal to the program data.

19. The memory device of claim 18, wherein the level-controlled program current is a pulse current applied to the selected resistance-variable memory cell during each iterative application.

20. The memory device of claim 19, wherein the generator comprises a pulse current selection circuit configured to select between at least one RESET pulse current and a SET pulse current on the basis of the program data.

21. The memory device of claim 19, wherein the pulse current is increased in an up staircase pattern with each successive iterative application.

22. The memory device of claim 18, wherein the memory array comprises a transistor configured to receive a high voltage provided by a high voltage generation circuit, be controlled by a bias voltage provided by the generator, and output the level-controlled program current in response to the high voltage and the bias voltage.

23. The memory device of claim 22, wherein the high voltage generation circuit comprises a charge pump.

24. The memory device of claim 22, wherein the level-controlled program current output by the transistor is applied to a data line connected to the selected resistance-variable memory cell.

25. The memory device of claim 22, wherein the data line connected to the selected resistance-variable memory cell is a bit line.

26. A memory device comprising:

an array of resistance-variable memory cells divided into a first memory block including a first selected memory cell and a second memory block including a second selected memory cell;

sensing and writing circuitry configured to simultaneously program the first and second selected memory cells with program data by iteratively applying a level-controlled program current to the first and second selected memory cells, and performing a verify read operation on the first and second selected memory cells until respective programmed states for the first and second memory cells are equal to the program data.

27. The device of claim 26, wherein prior to the simultaneous programming of the first and second selected memory cells, each one of the first and second memory blocks receives a reference voltage.

28. The device of claim 27, wherein the reference voltage is generated by a precharge circuit.