Signal interleaving for serial clock and data recovery

• US 8,160,192 B2
• Filed: 09/25/2007
• Issued: 04/17/2012
• Est. Priority Date: 09/25/2006
• Status: Active Grant

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Silicon Image, Inc. (Lattice Semiconductor Corporation)
• Inventors: Lee, Dongyun, Kim, Sungjoon
• Primary Examiner(s): Timory, Kabir A
• Application Number:
  US11/861,175
• Publication Number:
  US 20080075222A1
• Time in Patent Office: 1,666 Days
• Field of Search: 375/354, 375/326, 375/373, 375/376, 375/215, 375/294
• US Class Current: 375/354
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0816 the controlled phase shifter and the frequency- or phase-detection arrangement being connected to a common input
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A clock and data recovery (CDR) system and method for recovering timing information and data from a serial data stream. The CDR system includes a sampling circuit that produces a recovered clock/data signal and an interleaving feedback network that provides feedback to the sampling circuit. The feedback network includes a logic circuit that produces control signals based on the recovered clock/data signal, a first multiplexer that selects from four phases of a global clock signal based on a control signal, a first delay-locked loop having a first set of delay cells coupled to a second multiplexer that produces a delayed signal based on the selected global clock signal, and a second delay-locked loop having a second set of delay cells that produces a set of phase-shifted feedback signals that are applied to the sampling circuit to phase-align the sampling circuit with the transitions in the received serial data stream.

Claims

1. A system for recovering timing information from a serial data stream, comprising:

a sampling circuit that produces a recovered data signal by using one or more feedback signals of a plurality of feedback signals to sample a serial data stream; and

an interleaving feedback network that produces the plurality of feedback signals, comprising;

a control circuit that produces control signals based on the recovered data signal;

a first multiplexer that is coupled to receive a plurality of periodic signals and select an individual periodic signal based on a first control signal from the control circuit;

a first delay-locked loop having a first series of delay cells that produce a plurality of delayed signals based on the selected periodic signal;

a second multiplexer that is coupled to receive the plurality of delayed signals and selects an individual delayed signal as based on a second control signal from the control circuit; and

a second delay-locked loop coupled with the second multiplexer and having a second series of delay cells that produces the plurality of feedback signals based on the selected delayed signal, wherein the second delay-locked loop further includes a third multiplexer that is coupled to receive a third control signal from the control circuit, the third multiplexer causing the second delay-locked loop to enter either an open mode of operation or a closed mode of operation in response to the third control signal.

2. The system of claim 1 wherein the first series of delay cells comprises M delay cells, wherein M is a value selected from the series (2ⁿ−

1) for positive integer values of n.

3. The system of claim 2 wherein the individual periodic signals have a period T₁ and have offset phases of unit interval T₁/N, wherein N is the number of individual periodic signals received by the first multiplexer.

4. The system of claim 3 wherein the control circuit is configured to control the first and second multiplexers so that the plurality of delayed signals have an incremental resolution of T₁/(N×

M).

5. The system of claim 1, wherein the closed mode of operation is entered when the one of the plurality of periodic signals is selected in response to the first control signal from the control circuit.

6. The system of claim 1, wherein the closed mode of operation is entered when the one of the plurality of delayed signals is selected in response to the second control signal from the control circuit.

7. A method for recovering timing information from a serial data stream, the method comprising:

selecting one of a plurality of periodic signals based on a data signal associated with a serial data stream that is recovered by a sampling circuit;

delaying the selected periodic signal to produce a plurality of delayed signals, wherein the plurality of delayed signals are produced by a first delay-locked loop;

selecting one of the first plurality of delayed signals based on the recovered data signal;

delaying the selected delay signal to produce a plurality of feedback signals, wherein the plurality of feedback signals are produced by a second delay-locked loop, wherein the second delay-locked loop includes a first multiplexer receiving a control signal from a control circuit;

using one or more of the plurality of feedback signals as feedback for the sampling circuit that produces the recovered data signal in order to phase-align to transitions in the data stream; and

placing the second delay-locked loop in either an open mode of operation or a closed mode of operation in response to the control signal received by the first multiplexer from the control circuit.

8. The method of claim 7 wherein each of the plurality of periodic signals corresponds to an individual phase of a global clock signal, and wherein the plurality of periodic signals further comprise N individual periodic signals having a period T₁, and being offset from each other by a phase difference of T₁/N.

9. The method of claim 8 wherein delaying the selected periodic signal to produce the plurality of delayed signals further comprises producing M individual delayed signals based on one of the N individual periodic signals, wherein the M individual delayed signals are offset from each other by a phase difference of T₁/M, and wherein M is a value selected from the series (2ⁿ−

1) for positive integer values of n.

10. The method of claim 9 wherein the first delay-locked loop includes a first series of M delay cells, the first series of delay cells producing the plurality of delayed signals.

11. The method of claim 10 wherein selecting the one of the first plurality of delayed signals further comprises controlling the operation of a second multiplexer that couples one of the N individual periodic signals to the first delay-locked loop, and wherein selecting one of the periodic signal phases comprises controlling the operation of a third multiplexer that couples one of the M individual delayed signals to the second delay-locked loop.

12. The method of claim 10 wherein the second delay-locked loop includes a second series of delay cells, the second series of delay cells producing the plurality of feedback signals.

13. The method of claim 7, wherein placing the second delay-locked loop in a closed mode of operation comprises entering the closed mode of operation when selecting the one of the plurality of periodic signals or when selecting the one of the plurality of delayed signals.

14. A serial clock data recovery circuit, comprising:

a reference clock providing a plurality of clock signals having different phases;

a first delay-locked loop coupled to the reference clock and generating a plurality of delayed signals from a selected one of the plurality of clock signals;

a second delay-locked loop coupled to the first delay-locked loop and generating a plurality of feedback signal signals from a selected one of the plurality of delayed signals;

a sampler array receiving the feedback signal from the second delay-locked loop, wherein the sampler array uses one or more of the plurality of feedback signals to sample an incoming serial bit stream and recover serial data, the sampler array further outputting signals that are used to select the one of the plurality of clock signals and the one of the plurality of delayed signals;

a control circuit for receiving the signals output from the sampler array and generating a plurality of control signals; and

a first switch coupled to the second delay-locked loop and the control circuit, the first switch causing the second delay-locked loop to enter either an open mode of operation or a closed mode of operation in response to a first control signal from the control circuit.

15. The serial clock data recovery circuit of claim 14, wherein the first delay-locked loop is comprised of a plurality of delay cells and wherein each of the plurality of delayed signals is generated by a corresponding one of the plurality of delay cells.

16. The serial clock data recovery circuit of claim 14, further comprising a second switch coupled to the reference clock and to the control circuit, the second switch selecting the one of the plurality of clock signals in response to a second control signal from the control circuit.

17. The serial clock data recovery circuit of claim 16, further comprising a third switch coupled to the first delay-locked loop and to the control circuit, the third switch selecting the one of the first plurality of delay signals in response to a third control signal from the control circuit.

18. The serial clock data recovery circuit of claim 14, wherein the closed mode of operation is entered when one of the plurality of clock signals is selected in response to one of the plurality of control signals from the control circuit.

19. The serial clock data recovery circuit of claim 14, wherein the closed mode of operation is entered when one of the first plurality of delay signals is selected in response to one of the plurality of control signals from the control circuit.

20. The serial clock data recovery circuit of claim 14, wherein the closed mode of operation is entered for less than two cycles of the selected one of the plurality of clock signals.

21. The serial clock data recovery circuit of claim 14, wherein the second delay-locked loop is comprised of a plurality of delay cells and wherein the plurality of feedback signals is generated by the plurality of delay cells and provided to the sampler array.