Audio output circuits having ramped attenuation circuits that inhibit pop disturbances when audio sources are switched

• US 8,160,272 B1
• Filed: 07/15/2008
• Issued: 04/17/2012
• Est. Priority Date: 07/15/2008
• Status: Active Grant

• Current Assignee: Tempo Semiconductor, Inc.
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Blackburn, Jeffrey, Kanji, Ajaykumar
• Primary Examiner(s): Louie, Wai-Sing
• Assistant Examiner(s): Tang, Suian
• Application Number:
  US12/173,564
• Time in Patent Office: 1,372 Days
• Field of Search: 381/56, 381/58, 381/59, 381/94.1, 381/94.5, 381/104, 381/109
• US Class Current: 381/94.5
• CPC Class Codes: H03G 3/348 Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits

Abstract

An audio output circuit includes a port attenuation circuit, which is configured to convert an abrupt dc voltage offset transition between a pair of audio signals received in sequence at an input thereof into a more gradual transition. This conversion is achieved by performing, in sequence, a ramp-to-mute operation on a first of the pair of audio signals and a ramp-from-mute operation on a second of the pair of audio signals. The ramp-to-mute operation includes ramping an output of the audio output circuit from a dc voltage offset associated with the first of the pair of audio signals to a reference dc voltage offset. The ramp-from-mute operation includes ramping the output of the audio output circuit from the reference dc voltage offset to a dc voltage offset associated with the second of the pair of audio signals. These ramping operations may be performed using voltage steps having uniform step size.

Claims

1. An audio output circuit, comprising:

a plurality of audio sources having outputs maintained at unequal dc voltage offsets when driven with respective audio signals;

an audio signal selection circuit electrically coupled to the outputs of said plurality of audio sources, said audio signal selection circuit configured to route an audio signal from a selected one of said plurality of audio sources to an output thereof; and

a port attenuation circuit electrically coupled to the output of said audio signal selection circuit, said port attenuation circuit configured to convert an abrupt dc voltage offset transition between a pair of audio signals received in sequence from said audio signal selection circuit into a more gradual transition that meets a pop disturbance threshold, said port attenuation circuit comprising;

a port attenuation control circuit configured to generate an active ramp enable signal during an operation to change the selected one of said plurality of audio sources output by said audio signal selection circuit; and

an attenuation switch network responsive to the ramp enable signal and an audio signal that is output from said audio signal selection circuit;

wherein the abrupt dc voltage offset transition exceeds the pop disturbance threshold;

wherein said port attenuation circuit is configured to convert the abrupt dc voltage offset transition into a more gradual transition that meets a pop disturbance threshold by performing ramp-to-mute and ramp-from-mute operations in sequence in said attenuation switch network, said ramp-to-mute and ramp-from-mute operations comprising ramping a first non-zero dc voltage offset associated with a first audio signal to a mute condition and then ramping a dc voltage associated with the mute condition to a second non-zero dc voltage offset associated with a second audio signal, which is unequal to the first non-zero dc offset voltage;

wherein said attenuation switch network comprises a series string of resistors having a first terminal configured to receive the audio signal output from said audio signal selection circuit during the ramp-to-mute and ramp-from-mute operations and a second terminal electrically coupled a reference voltage; and

wherein the dc voltage associated with the mute condition is unequal to the first and second non-zero dc voltage offsets.

2. The circuit of claim 1, wherein said port attenuation circuit is further configured to perform the ramp-from-mute operation by ramping the dc voltage associated with the mute condition to the second non-zero dc voltage offset associated with the second audio signal when the second audio signal has a dc signal component but no ac signal component during the ramp-from-mute operation.

3. The circuit of claim 1, wherein the first terminal of the series string of resistors is electrically coupled by a ramp transmission gate to the output of said audio signal selection circuit.

4. The circuit of claim 3, wherein said attenuation switch network further comprises a bypass transmission gate having an input electrically coupled to the output of said audio signal selection circuit and an output electrically coupled to an output of said attenuation switch network.

5. The circuit of claim 4, wherein said attenuation switch network further comprises a mute transmission gate having an input electrically coupled to the output of said attenuation switch network and an output electrically coupled to the reference voltage.

6. The circuit of claim 1, wherein said ramping a first non-zero dc voltage offset associated with a first audio signal to a mute condition comprises ramping the first non-zero dc voltage offset voltage steps having uniform step size.

7. The circuit of claim 6, wherein said port attenuation control circuit is further configured to generate a multi-bit count signal in response to a clock signal and a mute signal received by said port attenuation circuit.

8. The circuit of claim 7, wherein said port attenuation control circuit comprises:

a counter configured to generate the multi-bit count signal in response to the mute signal and the clock signal; and

a decoder responsive to the multi-bit count signal.