Method and system for a RFIC master
First Claim
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1. A method for handling operation of circuitry, comprising:
- configuring an on-chip programmable device that functions as a master on a first bus, wherein the first bus comprises a second bus and a third bus, wherein the second bus and the third bus are coupled via a bridge, wherein the second bus is a high speed bus and the third bus is a low speed bus, wherein the on-chip programmable device comprises a high-speed second bus interface that interfaces the second bus and a low-speed third bus interface that interfaces the third bus, wherein at least one interface to another device is coupled to the third bus, wherein the on-chip programmable device is programmed by a processor via the high-speed second bus interface, the processor directly accessing the second bus, the on-chip programmable device directly accessing the second bus and directly accessing the third bus;
controlling the another device coupled to the at least one interface via at least one signal generated by the on-chip programmable device; and
communicating the at least one generated signal via the third bus to the at least one interface when the on-chip programmable device receives an input timer signal, wherein the input timer signal includes a count that correlates to a number of wideband code division multiple access (WCDMA) chip periods.
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Abstract
Methods and systems for a RFIC master are disclosed. Aspects of one method may include configuring an on-chip programmable device that may function as a master on a bus that has at least one device interface, for example, RFIC interface, coupled to the bus. The on-chip programmable device may generate at least one signal to control at least one device coupled to at least one device interface. The on-chip programmable device may communicate the generated signal via the bus upon receiving an input timer signal and may be configured by writing at least one event data and an index-sample data to the on-chip programmable device. The index-sample data may comprise at least a count value and an event data index. When the count value equals a value of the timer signal, event data may be fetched and executed starting with the one specified by the event data index.
75 Citations
20 Claims
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1. A method for handling operation of circuitry, comprising:
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configuring an on-chip programmable device that functions as a master on a first bus, wherein the first bus comprises a second bus and a third bus, wherein the second bus and the third bus are coupled via a bridge, wherein the second bus is a high speed bus and the third bus is a low speed bus, wherein the on-chip programmable device comprises a high-speed second bus interface that interfaces the second bus and a low-speed third bus interface that interfaces the third bus, wherein at least one interface to another device is coupled to the third bus, wherein the on-chip programmable device is programmed by a processor via the high-speed second bus interface, the processor directly accessing the second bus, the on-chip programmable device directly accessing the second bus and directly accessing the third bus; controlling the another device coupled to the at least one interface via at least one signal generated by the on-chip programmable device; and communicating the at least one generated signal via the third bus to the at least one interface when the on-chip programmable device receives an input timer signal, wherein the input timer signal includes a count that correlates to a number of wideband code division multiple access (WCDMA) chip periods. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A mobile wireless communication device, comprising:
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a configurable, on-chip programmable device that functions as a master on a first bus, wherein the first bus includes a second bus and a third bus, wherein the second bus and the third bus are coupled via a bridge, wherein the second bus is a high speed bus and the third bus is a low speed bus, wherein the on-chip programmable device includes a high-speed second bus interface that directly interfaces the second bus and a low-speed third bus interface that directly interfaces the third bus, wherein at least one interface to another device is coupled to the third bus, wherein the configurable, on-chip programmable device is programmed by a processor via the high-speed second bus interface, the processor directly accessing the second bus, the on-chip programmable device directly accessing the second bus and directly accessing the third bus; and the another device coupled to the at least one interface, wherein the another device is controlled by at least one signal generated by the on-chip programmable device, wherein the at least one generated signal is communicated via the third bus to the at least one interface when the configurable, on-chip programmable device receives a timer signal, and wherein the timer signal includes a count that correlates to a number of wide-band code divisional multiple access (WCDMA) chip periods.
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19. A wireless cellular device, comprising:
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a configurable, on-chip programmable device that functions as a master on a first bus, wherein the first bus includes a second bus and a third bus, wherein the second bus and the third bus are coupled via a bridge, wherein the second bus is a high speed bus and the third bus is a low speed bus, wherein the on-chip programmable device includes a high-speed second bus interface that directly interfaces the second bus and a low-speed third bus interface that directly interfaces the third bus, wherein at least one interface to another device is coupled to the third bus, wherein the configurable, on-chip programmable device is programmed by a processor via the high-speed second bus interface, the processor directly accessing the second bus, the on-chip programmable device directly accessing the second bus and directly accessing the third bus; and the another device coupled to the at least one interface, wherein the another device is controlled by at least one signal generated by the on-chip programmable device, wherein the at least one generated signal is communicated via the third bus to the at least one interface when the configurable, on-chip programmable device receives a timer signal, and wherein the timer signal includes a count that correlates to a number of wide-band code divisional multiple access (WCDMA) chip periods. - View Dependent Claims (20)
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Specification
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Current AssigneeAvago Technologies International Sales Pte Limited (Broadcom, Inc.)
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Original AssigneeBroadcom Corporation (Broadcom, Inc.)
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InventorsHayem, Frederic, du Preez, Andrew, Botha, Louis, Conroy, Johan (Hendrik)
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Primary Examiner(s)Zaman, Faisal M
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Application NumberUS13/186,311Publication NumberTime in Patent Office273 DaysField of Search710/110, 710306-315, 712/37, 712/38, 455/418, 455/419, 455/552.1, 455/553.1US Class Current710/110CPC Class CodesG06F 13/4221 being an input/output bus, ...
