Correction of single event upset error within sequential storage circuitry of an integrated circuit

• US 8,161,367 B2
• Filed: 10/07/2008
• Issued: 04/17/2012
• Est. Priority Date: 10/07/2008
• Status: Active Grant

• Current Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Original Assignee: Arm Ltd. (United Kingdom) (SoftBank Group Corp.)
• Inventors: Chandra, Vikas
• Primary Examiner(s): Gaffin, Jeffrey A
• Assistant Examiner(s): NGUYEN, STEVE N
• Application Number:
  US12/285,517
• Publication Number:
  US 20100088565A1
• Time in Patent Office: 1,288 Days
• Field of Search: 714/726, 714/819, 714/822, 714/823, 326 9- 12
• US Class Current: 714/822
• CPC Class Codes: G06F 11/183 by voting, the voting not being performed by the redundant components
• CPC Class Codes: H03K 19/00392 by circuit redundancy H03K19/0075 takes precedence

Abstract

Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error in any of the first and second storage elements. Two additional storage elements are provided for storing third and fourth indications of the input data value respectively in response to a pulse signal derived from the clock signal. Included is comparison circuitry for comparing the third and fourth indications of the input data value and further comparison circuitry for comparing, during a first phase of the clock signal, the first indication and at least one of the third and fourth indications, and for comparing, during a second phase of the clock signal, the second indication and at least one of the third and fourth indications.

Claims

1. Sequential storage circuitry for an integrated circuit, comprising:

storage circuitry comprising;

a first storage element for storing, during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry;

a second storage element coupled to an output of said first storage element, for storing a second indication of said input data value during a second phase of said clock signal; and

error detection circuitry for detecting a single event upset error in any of said first and second storage elements comprising;

two additional storage elements for storing third and fourth indications of said input data value respectively in response to a pulse signal derived from said clock signal;

comparison circuitry for comparing said third and fourth indications of said input data value; and

further comparison circuitry for comparing during a first phase of said clock signal said first indication and at least one of said third and fourth indications, and for comparing during a second phase of said clock signal said second indication and at least one of said third and fourth indications; and

output circuitry for correcting any detected errors in said storage circuitry and for outputting an output value;

said output circuitry being responsive to no match by said comparison circuitry to output said first indication during a first phase of said clock signal and said second indication during said second phase of said clock signal, and

said output circuitry being responsive to a match by said comparison circuitry to output a value in dependence upon comparisons performed by said further comparison circuitry;

said output circuitry being responsive to a match by said further comparison circuitry during a first phase of said clock signal to output said first indication during said first clock cycle and to a no match to output an inverted value of said first indication; and

said output circuitry being responsive to a match by said further comparison circuitry during a second phase of said clock signal to output said second indication during said second phase of said clock signal and to a no match to output an inverted value of said second indication.

2. Sequential storage circuitry according to claim 1, comprising error detection signal generation circuitry for combining an output of said comparison circuitry and said further comparison circuitry to generate an error or no_error signal to be sent to said output circuitry, wherein said comparison circuitry comprises circuitry responsive to a difference in said third and fourth indications to output an error_mask signal to said error detection signal generation circuitry, said error detection signal generation circuitry being responsive to said error_mask signal to generate a no_error signal, said output circuitry being responsive to said no_error signal not to correct an output of said storage circuitry, said output of said storage circuitry comprising said first indication during a first phase of said clock cycle and said second indication during a second phase of said clock cycle.

3. Sequential storage circuitry according to claim 2, wherein said error detection signal generation circuitry is responsive to a difference in an output of either said third or fourth indication and an output of said storage circuitry detected by said further comparison circuitry and to no receipt of an error_mask signal to generate said error signal, said output circuitry being responsive to said error signal to correct an output of said storage circuitry by inverting said output.

4. Sequential storage circuitry according to claim 3, wherein said comparison circuitry output path to said error detection signal generation circuitry is shorter than said output path of said further comparison means to said error detection signal generation circuitry such that said further circuitry receives said comparison result of said comparison circuitry before said comparison result of said further comparison circuitry.

5. Sequential storage circuitry according to claim 1, wherein said storage circuitry comprises a master slave flip flop, said first storage element comprising said master latch and said second storage element comprising said slave latch.

6. Sequential storage circuitry according to claim 1, wherein a data output path for outputting data from said storage circuitry to said output circuitry and an error correction path comprising said further comparison circuitry and a path for outputting a no match signal from said further comparison circuitry to said output circuitry are balanced such that in response to an output from said storage circuitry switching value due to said single event error, said output circuitry receives said switched value at about a same time as said no match signal.

7. Sequential storage circuitry according to claim 1, wherein said comparison circuitry output path to said output circuitry is shorter than said output path of said further comparison means to said output circuitry such that said output circuitry receives said comparison result of said comparison circuitry before said comparison result of said further comparison circuitry.

8. Sequential storage circuitry according to claim 1, wherein said output circuitry comprises an inverter for inverting a signal output by said storage circuitry, said storage circuitry outputting said first indication during a first phase of said clock cycle and said second indication during a second phase of said clock cycle and a multiplexer for selecting between said output signal or said inverted output signal in response to an error detection signal output by said error detection circuitry.

9. Sequential storage circuitry according to claim 8, wherein said error detection circuitry comprises error detection signal generation circuitry for generating said error detection signal in response to a match signal from said comparison circuitry and a no match signal from said further comparison circuitry.

10. An integrated circuit comprising a plurality of sequential storage circuitry elements according to claim 1, and a clock pulse generator for generating a clock pulse in response to a start of said first phase of said clock signal, said clock pulse generator supplying said clock pulse to said plurality of sequential storage circuitry elements.

11. An integrated circuit according to claim 10, and further comprising combinatorial circuitry interposed between said plurality of sequential storage elements.

12. A method of correcting a single event upset error in sequential storage circuitry of an integrated circuit, said sequential storage circuitry of said integrated circuitry comprising a first storage element and a second storage element coupled to an output of said first storage element, and a third and fourth storage element the method comprising the steps of:

storing in said first storage element during a first phase of a clock signal, a first indication of an input data value received by said sequential storage circuitry;

storing in said second storage element during a second phase of said clock signal a second indication of said input data value;

storing in said third and fourth storage elements on occurrence of a pulse signal derived from said clock signal, a respective third and fourth indication of said input data value;

detecting a single event upset error in any of said storage elements by;

(i) comparing said third and fourth indication and in response to a difference detecting said single event upset error is in said third or fourth storage elements;

(ii) comparing during said first phase of said clock signal said input data value as indicated by said first indication and at least one of said third and fourth indication of said input value and if there is a difference and step (i) found no difference, detecting said single event upset error is in said first storage element; and

(iii) comparing during said second phase of said clock signal said input data value as indicated by said second indication and at least one of said third and fourth indication of said input value and if there is a difference and step (i) found no difference, detecting said single event upset error is in said second storage element; and

correcting in an output value a detected single event upset error in said first or second storage elements and outputting said output value by;

during said first phase of said clock signal either;

outputting said first indication of said input value in response to detection of no single event upset error in said first storage element;

or

outputting an inverted value of said first indication of said input value in response to detection of a single event upset error in said first storage element; and

during said second phase of said clock signal either;

outputting said second indication of said input value in response to detection of no single event upset error in said second storage element;

or

outputting an inverted value of said second indication of said input value in response to detection of no single event upset error in said second storage element.

13. A sequential storage means comprising:

a storage means for storing an indication of data received in a first storage element during a first phase of a clock signal, and for storing an indication of said data in a second storage element during a second phase of said clock signal;

a further third and fourth storage means for storing an indication of said data in response to a pulse signal derived from said clock signal;

error detecting means for detecting a single event upset error in said storage means by;

detecting said single event upset error in said third or fourth storage means if there is a difference in said stored value; and

if there is no difference

detecting said single event upset error in said first storage element if during said first phase of said clock signal there is a difference in said stored value and at least one of said stored values in said third and fourth storage means; and

detecting said single event upset error in said second storage element if during said second phase of said clock signal there is a difference in said stored value and at least one of said stored values in said third and fourth storage means; and

output means for correcting in an output value said single event upset error occurring in said first or second storage elements and outputting said output value, said output means comprising;

correction means for inverting a value output by said storage means in response to detection of a single event upset error in either said first or said second storage elements and not inverting said value in response to no detection of said single event upset error.

14. A sequential storage means according to claim 13, wherein said storage means is for outputting said indication of data received in said first storage element during said first phase of a clock signal, and for outputting an indication of said data in said second storage element during a second phase of said clock signal.

15. A sequential storage means according to claim 14, wherein said output means comprises an inverting means for inverting said value output by said storage means and a selecting means for selecting said inverted value in response to detection of a single event upset error in either said first or said second storage elements and for selecting said output value in response to no detection of said single event upset error.