Automated processor generation system and method for designing a configurable processor

• US 8,161,432 B2
• Filed: 10/09/2008
• Issued: 04/17/2012
• Est. Priority Date: 02/17/2000
• Status: Active Grant

• Current Assignee: Tensilica Incorporated
• Original Assignee: Tensilica Incorporated
• Inventors: Wang, Albert Ren-Rui, Ruddell, Richard, Goodwin, David William, Bhattacharyya, Nupur, Medina, Marines Puig, Lichtenstein, Walter David, Konas, Pavlos, Srinivasan, Rangarajan, Songer, Christopher Mark, Parameswar, Akilesh, Maydan, Dror E., Gonzalez, Ricardo E., Killian, Earl A.
• Primary Examiner(s): Do, Thuan
• Application Number:
  US12/248,890
• Publication Number:
  US 20090177876A1
• Time in Patent Office: 1,286 Days
• Field of Search: 716/101, 716/113, 716/116
• US Class Current: 716/101
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants

Abstract

A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.

Claims

1. A computer-implemented system for designing a configurable processor, the system comprising:

hardware generation means for, based on a user-defined specification, generating a description of a hardware implementation of the processor; and

software generation means for, based on the user-defined specification, generating software development tools specific to the hardware implementation;

wherein the user-defined specification includes a user-defined specification of a processor exception and when a processor instruction raises the exception; and

the hardware generation means includes user-defined exception support generating means for generating hardware supporting the user-defined specification of the processor exception as part of the processor hardware implementation.

2. A computer-implemented system according to claim 1, wherein the user-defined specification of the processor exception includes priority information associated with the processor exception.

3. A computer-implemented system according to claim 2, wherein the user-defined exception support generating means includes means for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals in accordance with the priority information.

4. A computer-implemented system according to claim 1, wherein the user-defined exception support generating means includes means for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

5. A computer-implemented system according to claim 1, wherein the user-defined exception support generating means includes means for encoding a signal from the hardware supporting the user-defined specification of the processor exception with a priority level.

6. A computer-implemented system according to claim 1, wherein the user-defined exception support generating means includes means for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

7. A computer-implemented system according to claim 1, wherein the user-defined specification of the processor exception includes a schedule declaration associated with when the processor instruction raises the exception.

8. A computer-implemented system according to claim 7, wherein the schedule declaration includes a pipeline stage associated with execution of the instruction.

9. A computer-implemented method for designing a configurable processor, the system comprising:

based on a user-defined specification, generating a description of a hardware implementation of the processor; and

based on the user-defined specification, generating software development tools specific to the hardware implementation;

wherein the user-defined specification includes a user-defined specification of a processor exception and when a processor instruction raises the exception; and

the hardware generation step includes generating hardware supporting the user-defined specification of the processor exception as part of the processor hardware implementation.

10. A computer-implemented method to claim 9, wherein the user-defined specification of the processor exception includes priority information associated with the processor exception.

11. A computer-implemented method according to claim 10, wherein the hardware generating step includes generating hardware for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals in accordance with the priority information.

12. A computer-implemented method according to claim 9, wherein the hardware generating step includes generating hardware for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

13. A computer-implemented method according to claim 9, wherein the hardware generating step includes generating hardware for encoding a signal from the hardware supporting the user-defined specification of the processor exception with a priority level.

14. A computer-implemented method according to claim 9, wherein the hardware generating step includes generating hardware for combining a signal from the hardware supporting the user-defined specification of the processor exception with other processor exception signals.

15. A computer-implemented method according to claim 9, wherein the user-defined specification of the processor exception includes a schedule declaration associated with when the processor instruction raises the exception.

16. A computer-implemented method according to claim 15, wherein the schedule declaration includes a pipeline stage associated with execution of the instruction.