Method for forming NAND typed memory device
First Claim
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1. A method for fabricating a NAND type flash memory device comprising:
- defining a select transistor region and a memory cell region in a semiconductor substrate;
forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over the semiconductor substrate;
etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer in the select transistor region;
forming a low resistance layer over inner sidewalls and a bottom of the opening;
forming a barrier metal layer in a remaining region of the opening after forming the low resistance layer, wherein a top surface of the floating gate is in contact with a bottom surface of the barrier metal layer;
forming a control gate conductive layer over the semiconductor substrate, wherein a bottom surface of the control gate is in contact with a top surface of the barrier metal layer, thereby electrically connecting the floating gate to the control gate by the barrier metal layer and the low resistance layer; and
etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer, thereby forming gate stacks of memory cells and source/drain select transistors.
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Abstract
A method for fabricating a NAND type flash memory device includes defining a select transistor region and a memory cell region in a semiconductor substrate, forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over a semiconductor substrate, etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer, forming a low resistance layer in the opening, forming a control gate conductive layer over the semiconductor substrate, and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer to form gate stacks of memory cells and source/drain select transistors.
17 Citations
11 Claims
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1. A method for fabricating a NAND type flash memory device comprising:
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defining a select transistor region and a memory cell region in a semiconductor substrate; forming a tunnel insulating layer, a floating gate conductive layer, and a dielectric layer over the semiconductor substrate; etching the dielectric layer, thereby forming an opening exposing the floating gate conductive layer in the select transistor region; forming a low resistance layer over inner sidewalls and a bottom of the opening; forming a barrier metal layer in a remaining region of the opening after forming the low resistance layer, wherein a top surface of the floating gate is in contact with a bottom surface of the barrier metal layer; forming a control gate conductive layer over the semiconductor substrate, wherein a bottom surface of the control gate is in contact with a top surface of the barrier metal layer, thereby electrically connecting the floating gate to the control gate by the barrier metal layer and the low resistance layer; and etching the control gate conductive layer, the dielectric layer, the floating gate conductive layer, and the tunnel insulating layer, thereby forming gate stacks of memory cells and source/drain select transistors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Current AssigneeHynix Semiconductor Incorporated (SK Hynix Inc.)
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Original AssigneeHynix Semiconductor Incorporated (SK Hynix Inc.)
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InventorsKim, Nam-Kyeong, Woo, Won Sic
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Primary Examiner(s)Ahmadi, Mohsen
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Application NumberUS12/956,878Publication NumberTime in Patent Office511 DaysField of Search257/E21.69, 257/E21.294US Class Current438/257CPC Class CodesH10B 41/30 characterised by the memory...H10B 41/35 with a cell select transist...
