Non-diffusion junction split-gate nonvolatile memory cells and arrays, methods of programming, erasing, and reading thereof, and methods of manufacture

• US 8,164,135 B2
• Filed: 05/04/2010
• Issued: 04/24/2012
• Est. Priority Date: 07/10/2007
• Status: Active Grant

• Current Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Original Assignee: Silicon Storage Technology Incorporated (Microchip Technology Incorporated)
• Inventors: Chen, Changyuan, Lin, Ya-Fen, Lee, Dana
• Primary Examiner(s): Parker, Kenneth
• Assistant Examiner(s): Page, Dale E
• Application Number:
  US12/773,811
• Publication Number:
  US 20100220533A1
• Time in Patent Office: 721 Days
• Field of Search: 257/316, 257/315, 257/319, 257/E21.68
• US Class Current: 257/316
• CPC Class Codes: G11C 16/0458 comprising two or more independent floating gates which store independent data
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: H01L 29/42328 with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H01L 29/42336 with one gate at least partly formed in a trench
• CPC Class Codes: H01L 29/7887 Programmable transistors with more than two possible different levels of programmation
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Claims

1. An array of flash memory structures, said array comprising:

a semiconductor substrate of a first conductivity type; and

a plurality of structures, each structure comprising;

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced, in a first direction, by application of voltage to gate elements disposed above the channel region;

a plurality of floating gates, spaced apart from one another, each insulated from the channel region;

a plurality of T-shaped control gates, spaced apart from one another, each insulated from the channel region, each control gate being laterally adjacent a first floating gate in position across, the channel region, being between the first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate, wherein each control gate and pair floating gates to which the control gate is capacitively coupled form a subcell; and

a plurality of assist gates, spaced apart from one another, each insulated from the channel region, each assist gate being between and insulated from a first subcell and a second subcell;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein structures adjacent to one another in a second direction, substantially perpendicular to the first direction, have the assist gate connected to one another in the first direction, and the control gate connected to one another in the second direction;

wherein operation of the second subcell as a programmed cell is enabled via electron flow induced in the first channel region, the second channel region, and the third channel region by voltages on the first floating gate associated with the first control gate, the assist gate, and the second control gate, respectively.

2. The array of claim 1 wherein a line of substrate region (bit line) laying beneath a row of control gates in a second direction includes an actual diffused junction at an end of the line.

3. The array of claim 1 wherein, with regard to control gates adjacent to each other in the first direction, the channel region lies between a first substrate under a first control gate and a second substrate region under a second control gate.

4. The array of claim 1 wherein each floating gate is between a control gate and an assist gate.

5. The array of claim 1 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.

6. The array of claim 5 wherein the floating gate is disposed adjacent the substrate, a control gate, and an assist gate, and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.

7. The array of claim 1 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.

8. The array of claim 7 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.

9. The array of claim 8 wherein each floating gate is located between an upper portion of a control gate and the channel region.

10. The array of claim 8 wherein each upper portion is immediately adjacent to one of the floating gates to which the control gate is capacitively coupled.

11. The array of claim 1 wherein the channel region defines a path used for one or both of reading or programming a floating gate.

12. The array of claim 1 wherein structures connected electrically to one another in series and co-linear to one another terminate at a first end and at a second end, with said first end addressed by a first address, and the second end addressed by a second address, different from the first address.

13. The array of claim 1 further comprising:

a plurality of active regions in continuous strips parallel to one another in the first direction with an isolation region separating each pair of adjacent active regions;

wherein each of the assist gates connecting one structure to an adjacent structure in the second direction crosses an isolation region; and

wherein each of the control gate connecting one structure to an adjacent structure in the second direction crosses an isolation region.

14. The array of claim 1 wherein the line of substrate region of a first structure is electrically connected to the first substrate region of a second structure adjacent to one side of the first structure in the second direction;

and

wherein the second substrate region of the first structure is electrically connected to the second substrate region of a third structure adjacent to another side of the first structure in the second direction.

15. The array of claim 14 wherein a line of electrically connected substrate regions laying beneath a row of control gates in a second direction includes an actual diffused junction at an end of the line.

16. An array of flash memory structures, said array comprising:

a semiconductor substrate of a first conductivity type; and

a plurality of structures, each structure comprising;

a non-diffused channel region within the semiconductor substrate through which electron flow may be induced, in a first direction, by application of voltage to gate elements disposed above the channel region;

a plurality of floating gates, spaced apart from one another, each insulated from the channel region;

a plurality of T-shaped control gates, spaced apart from one another, each insulated from the channel region, each control gate being laterally adjacent a first floating gate in position across, the channel region, being between the first floating gate and a second floating gate, and being capacitively coupled to the first floating gate and the second floating gate, wherein each control gate and pair floating gates to which the control gate is capacitively coupled form a subcell; and

a plurality of assist gates, spaced apart from one another, each insulated from the channel region, each assist gate being between and insulated from a first subcell and a second subcell;

wherein the channel region includes a first channel region beneath the first subcell, a second channel region beneath the second subcell, and a third channel region beneath the assist gate, and wherein each subcell and each assist gate control conductivity of a channel region located therebeneath;

wherein structures adjacent to one another in a second direction, substantially perpendicular to the first direction, have the assist gate connected to one another in the first direction, and the control gate connected to one another in the second direction;

wherein a read operation of the second subcell is enabled via electron flow induced in the first channel region, the second channel region, and the third channel region by voltages on the first floating gate associated with the first control gate, the assist gate, and the second control gate, respectively.

17. The array of claim 16 wherein a line of substrate region (bit line) laying beneath a row of control gates in a second direction includes an actual diffused junction at an end of the line.

18. The array of claim 16 wherein, with regard to control gates adjacent to each other in the first direction, the channel region lies between a first substrate under a first control gate and a second substrate region under a second control gate.

19. The array of claim 16 wherein each floating gate is between a control gate and an assist gate.

20. The array of claim 16 wherein each floating gate is immediately adjacent a channel region associated with the subcell in which the floating gate is located.

21. The array of claim 20 wherein the floating gate is disposed adjacent the substrate, a control gate, and an assist gate, and insulated therefrom with insulation material having a thickness that permits Fowler-Nordheim tunneling.

22. The array of claim 16 wherein the first T-shaped control gate is part of a passing cell and the second T-shaped control gate is part of a programmed cell.

23. The array of claim 22 wherein each control gate includes a lower portion immediately adjacent the channel region and two upper portions.

24. The array of claim 23 wherein each floating gate is located between an upper portion of a control gate and the channel region.

25. The array of claim 23 wherein each upper portion is immediately adjacent to one of the floating gates to which the control gate is capacitively coupled.

26. The array of claim 16 wherein the channel region defines a path used for one or both of reading or programming a floating gate.

27. The array of claim 16 wherein structures connected electrically to one another in series and co-linear to one another terminate at a first end and at a second end, with said first end addressed by a first address, and the second end addressed by a second address, different from the first address.

28. The array of claim 16 further comprising:

a plurality of active regions in continuous strips parallel to one another in the first direction with an isolation region separating each pair of adjacent active regions;

wherein each of the assist gates connecting one structure to an adjacent structure in the second direction crosses an isolation region; and

wherein each of the control gate connecting one structure to an adjacent structure in the second direction crosses an isolation region.

29. The array of claim 16 wherein the line of substrate region of a first structure is electrically connected to the first substrate region of a second structure adjacent to one side of the first structure in the second direction;

and

wherein the second substrate region of the first structure is electrically connected to the second substrate region of a third structure adjacent to another side of the first structure in the second direction.

30. The array of claim 29 wherein a line of electrically connected substrate regions laying beneath a row of control gates in a second direction includes an actual diffused junction at an end of the line.