Structure of power grid for semiconductor devices and method of making the same

• US 8,164,190 B2
• Filed: 06/25/2009
• Issued: 04/24/2012
• Est. Priority Date: 06/25/2009
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Filippi, Ronald, Li, Wai-kin, Wang, Ping-Chuan
• Primary Examiner(s): Nguyen, Ha Tran T
• Assistant Examiner(s): Tran, Thanh Y
• Application Number:
  US12/491,372
• Publication Number:
  US 20100327445A1
• Time in Patent Office: 1,034 Days
• Field of Search: 257/773, 257/774, 257/758, 257/751, 257/762, 257/763, 257/734, 438/622, 438/612, 438/613, 438/614, 438/620, 438/687, 438/688, 438/643, 438/653, 438/675, 438/672, 438/761, 438/645, 438/629, 438/627, 438/637, 438/625, 438/623, 438/618, 438/597
• US Class Current: 257/751
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76852 the layer also covering the sidewalls of the conductive structure
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53223 Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53252 Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53266 Additional layers associated with refractory-metal layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An embodiment of the invention provides a semiconductor structure, which may include a stud of a first conductive material formed inside a dielectric layer; a via of a second conductive material having a bottom and sidewalls with the bottom and the sidewalls being covered by a conductive liner, and the bottom being formed directly on top of the stud and being in contact with the via through the conductive liner; and one or more conductive paths of a third conductive material connecting to the via through the conductive liner at the sidewalls of said the. A method of making the semiconductor structure is also provided.

Claims

1. A semiconductor structure, comprising:

a stud of a first conductive material formed inside a dielectric layer;

a via of a second conductive material having a bottom and sidewalls, said bottom and said sidewalls being covered by a conductive liner, said bottom being formed on top of said stud and being in contact with said stud through said conductive liner; and

one or more conductive paths of a third conductive material connecting to said via through said conductive liner at said sidewalls of said via, wherein said one or more conductive paths being formed between said dielectric layer and a second dielectric layer on top thereof.

2. The semiconductor structure of claim 1, wherein conductivity of said second conductive material of said via is greater than conductivity of said conductive liner covering said via at said bottom and said sidewalls.

3. The semiconductor structure of claim 2, wherein a lateral dimension of said via measured by two of said sidewalls opposing each other is less than a Blech length, said Blech length being associated with a current density of 20 mA/μ

m² in said via.

4. The semiconductor structure of claim 3, wherein said first and said second conductive materials are selected from a group consisting of tungsten (W), aluminum (Al), copper (Cu), and alloy thereof, and said third conductive material is selected from a group consisting of aluminum (Al), copper (Cu), silver (Ag), gold (Au), and alloy thereof.

5. The semiconductor structure of claim 1, wherein said one or more conductive paths are embedded inside said dielectric layer and are directly surrounded by said dielectric layer at least at two sides and a bottom thereof.

6. The semiconductor structure of claim 1, wherein said conductive liner is made of a material being selected from a group consisting of titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), titanium-nitride (TiN), tantalum-nitride (TaN), ruthenium nitride (RuN), and tungsten nitride (WN), and wherein said conductive liner being capable of preventing conductive materials from diffusing therethrough.

7. The semiconductor structure of claim 1, wherein said stud is formed directly on top of a contact location of a semiconductor device formed in a substrate underneath said dielectric layer, said semiconductor device being a field-effect transistor with said contact location being a gate region, a source region, or a drain region of said field-effect transistor or a heterojunction bipolar transistor with said contact location being a base region, an emitter region, or a collector region of said heterojunction bipolar transistor.

8. A power grid comprising:

a dielectric layer formed on top of multiple semiconductor devices;

a plurality of conductive studs formed inside said dielectric layer and situated on top of said multiple semiconductor devices;

at least one via formed on top of one of said plurality of conductive studs, said via being covered at a bottom and sidewalls by a conductive liner, and said conductive liner being in direct contact with said one of said plurality of conductive studs; and

one or more conductive paths connecting to said via through said conductive liner, wherein said one or more conductive paths being formed between said dielectric layer and a second dielectric layer on top thereof.

9. The power grid of claim 8, wherein said plurality of conductive studs are formed from a first conductive material having a first conductivity;

said via is formed from a second conductive material having a second conductivity; and

said one or more conductive paths are formed from a third conductive material having a third conductivity, said second conductivity being greater than conductivity of said conductive liner covering said bottom and said sidewalls of said via.

10. The power grid of claim 9, wherein a lateral dimension of said via measured by two of said sidewalls opposing each other is less than a Blech length, said Blech length being associated with a current density of 20 mA/μ

m² in said via.

11. The power grid of claim 10, wherein said first and said second conductive materials are selected from a group consisting of tungsten (W), aluminum (Al), copper (Cu), and alloy thereof, and said third conductive material is selected from a group consisting of aluminum (Al), copper (Cu), silver (Ag), gold (Au), and alloy thereof.

12. The power grid of claim 8, wherein said one or more conductive paths are embedded inside said dielectric layer and are directly surrounded by said dielectric layer at least at two sides and a bottom thereof.

13. The power grid of claim 8, wherein said conductive liner is made of a material being selected from a group consisting of titanium (Ti), tantalum (Ta), ruthenium (Ru), tungsten (W), titanium-nitride (TiN), tantalum-nitride (TaN), ruthenium nitride (RuN), and tungsten nitride (WN), and wherein said conductive line being capable of preventing conductive materials from diffusing therethrough.

14. The power grid of claim 8, wherein at least one of said plurality of conductive studs is formed directly on top of a contact location of one of said multiple semiconductor devices formed in a substrate underneath said dielectric layer, said one of said multiple semiconductor devices being a field-effect transistor or a heterojunction bipolar transistor and said contact location being a gate region, a source region, or a drain region of said field-effect transistor or a base region, an emitter region, or a collector region of said heterojunction bipolar transistor.