Thin film transistor array, method for manufacturing the same and active matrix display
First Claim
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1. A thin film transistor array, comprising:
- an insulating substrate;
a plurality of thin film transistors, each of the thin film transistors comprising a source electrode, a drain electrode, a gate electrode and a semiconductor layer between the source electrode and the drain electrode;
anda plurality of sealing layers, each of the sealing layers being stripe-shaped, and each of the sealing layers covering the plurality of the thin film transistors and formed over the insulating substrate.
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Abstract
One embodiment of the present invention is a thin film transistor array including an insulating substrate, a plurality of thin film transistors and a sealing layer. The sealing layer is stripe-shaped and covers a plurality of the thin film transistors. The sealing layer is formed over the insulating substrate.
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Citations
19 Claims
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1. A thin film transistor array, comprising:
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an insulating substrate; a plurality of thin film transistors, each of the thin film transistors comprising a source electrode, a drain electrode, a gate electrode and a semiconductor layer between the source electrode and the drain electrode; and a plurality of sealing layers, each of the sealing layers being stripe-shaped, and each of the sealing layers covering the plurality of the thin film transistors and formed over the insulating substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A thin film transistor array, comprising:
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an insulating substrate; a plurality of thin film transistors, each of the thin film transistors, comprising; a gate electrode on the insulating substrate; a gate insulating layer; a source electrode and a drain electrode, the gate electrode overlapping the source electrode and the drain electrode through the gate insulating layer; a semiconductor layer between the source electrode and the drain electrode; a pixel electrode connected to the drain electrode; and a capacitor electrode, the pixel electrode overlapping the capacitor electrode through the gate insulating layer, the thin film transistors arranged in a matrix-shaped and being with a plurality of gate wires connected to a plurality of the gate electrodes and a plurality of source wires connected to a plurality of the source electrodes; and a plurality of sealing layers, each of the sealing layers formed over at least the semiconductor layer, each of the sealing layers being stripe-shaped over the insulating substrate and each of the sealing layers covering a plurality of the thin film transistors. - View Dependent Claims (14, 15, 16, 17, 18, 19)
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Specification