High performance eDRAM sense amplifier

• US 8,164,942 B2
• Filed: 02/01/2010
• Issued: 04/24/2012
• Est. Priority Date: 02/01/2010
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Gebara, Fadi H., Kuang, Jente B., Sivagnaname, Jayakumaran, Vo, Ivan
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US12/697,956
• Publication Number:
  US 20110188295A1
• Time in Patent Office: 813 Days
• Field of Search: 365/149, 365/189.05, 365/205, 365/207, 365/208
• US Class Current: 365/149
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/00 Arrangements for writing information into, or reading information out from, a digital store G11C5/00 takes precedence; auxiliary circuits for stores using semiconductor devices G11C11/4063, G11C11/413
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers

Abstract

Embedded dynamic random access memory (eDRAM) sense amplifier circuitry in which a bit line connected to each of a first plurality of eDRAM cells is controlled by cell control lines tied to each of the cells. During a READ operation the eDRAM cell releases its charge indicating its digital state. The digital charge propagates through the eDRAM sense amplifier circuitry to a mid-rail amplifier inverter circuit which amplifies the charge and provides it to a latch circuit. The latch circuit, in turn, inverts the charge to correctly represent at its output the logical value stored in the eDRAM cell being read, and returns the charge through the eDRAM sense amplifier circuitry to replenish the eDRAM cell.

Claims

1. An embedded dynamic random access memory (eDRAM) sense amplifier circuit comprising:

a first plurality of control lines each respectively connected to one of a plurality of eDRAM cells, wherein a first eDRAM cell is configured to release a charge indicating a digital state of the first eDRAM cell in response to a signal from a first control line of said first plurality of control lines;

a mid-rail amplifier circuit configured to amplify said charge indicating the digital state of the first eDRAM cell;

a latch circuit with an input connected to an output of the mid-rail amplifier circuit, an output of the latch circuit being connected to an output of the eDRAM sense amplifier; and

a writeback line connected to the output of the latch circuit.

2. The eDRAM sense amplifier circuit of claim 1, further comprising:

a bit line connected to each of the plurality of eDRAM cells including the first eDRAM cell;

wherein the writeback line connects the output of the latch circuit to the bit line.

3. The eDRAM sense amplifier circuit of claim 2, wherein the mid-rail amplifier circuit is in communication with said bit line.

4. The eDRAM sense amplifier circuit of claim 3, further comprising:

a capacitor connected in parallel with a transistor;

wherein the mid-rail amplifier circuit is in communication with said bit line via the capacitor connected in parallel with the transistor.

5. The eDRAM sense amplifier circuit of claim 4, further comprising:

a second plurality of transistor control lines configured to control transistors within the eDRAM sense amplifier circuit.

6. The eDRAM sense amplifier circuit of claim 5, wherein a value at the output of the latch circuit is returned back to the first eDRAM cell via the writeback line in response to changing the second plurality of transistor control lines from a first state to a second state.

7. The eDRAM sense amplifier circuit of claim 6, wherein said transistor in parallel with the capacitor is one of the transistors controlled by the second plurality of transistor control lines.

8. The eDRAM sense amplifier circuit of claim 1, wherein the charge indicating the digital state of the first eDRAM is a positive charge and the digital state is a logical “

1”

.

9. The eDRAM sense amplifier circuit of claim 2, wherein the writeback line connects the output of the latch circuit to the bit line via a transistor gate circuit comprising a pair of transistors connected in parallel, said pair of transistors being controlled by the second plurality of transistor control lines.

10. The eDRAM sense amplifier circuit of claim 1, wherein the charge is a first charge, the eDRAM sense amplifier circuit further comprising:

a second eDRAM cell configured to release a second charge on a bit line.

11. An eDRAM sense amplifier circuit, comprising:

a mid-rail amplifier circuit and configured to amplify a charge indicating a digital state of an eDRAM cell;

a latch circuit with an input in communication with an output of the mid-rail amplifier circuit, an output of the latch circuit being configured to provide a signal to an output of the eDRAM sense amplifier;

a capacitor connected in parallel with a transistor, wherein the mid-rail amplifier circuit is in communication with a bit line of the eDRAM cell via said capacitor in parallel with the transistor; and

a writeback line connecting the output of the latch circuit and the bit line.

12. The eDRAM sense amplifier circuit of claim 11, wherein said eDRAM cell is one of a plurality of eDRAM cells, the eDRAM sense amplifier circuit further comprising:

a first plurality of control lines each respectively controlling one of the plurality of eDRAM cells, wherein said eDRAM cell is configured to release the charge in response to a signal from a first control line of said first plurality of control lines.

13. The eDRAM sense amplifier circuit of claim 12, further comprising:

a second plurality of transistor control lines configured to control transistors within the eDRAM sense amplifier circuit;

wherein said transistor in parallel with the capacitor is one of the transistors controlled by the second plurality of transistor control lines.

14. The eDRAM sense amplifier circuit of claim 13, wherein a value at the output of the latch circuit is returned back to the eDRAM cell via the writeback line in response to changing the second plurality of transistor control lines from a first state to a second state.

15. The eDRAM sense amplifier circuit of claim 14, wherein the writeback line connects the output of the latch circuit to the bit line via a transistor gate circuit comprising a pair of transistors connected in parallel, said pair of transistors being controlled by the second plurality of transistor control lines.