Predictive DMA data transfer

• US 8,166,212 B2
• Filed: 06/26/2007
• Issued: 04/24/2012
• Est. Priority Date: 06/26/2007
• Status: Active Grant

• Current Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Original Assignee: Xerox Corporation (Xerox Holdings Corp.)
• Inventors: La, Louis Ba, Warner, Scott C., Nagarajan, Ramesh
• Primary Examiner(s): Lee, Chun-Kuan
• Assistant Examiner(s): MODO, RONALD T
• Application Number:
  US11/823,049
• Publication Number:
  US 20090002761A1
• Time in Patent Office: 1,764 Days
• Field of Search: 710/22
• US Class Current: 710/22
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: H04N 1/32571 Details of system components
• CPC Class Codes: H04N 2201/0091 Digital copier; digital 'photocopier' H04N2201/0093 and H04N2201/0094 take precedence

Abstract

A compression and storage device comprises: a compressor configured to compress data; a central processing unit (CPU) configured to control storage of the compressed data and to perform at least one additional task; an electronic memory organized as storage blocks each having a storage block size; a direct memory access (DMA) engine configured to operate autonomously from the CPU to transfer a current transfer block of compressed data into one or more storage blocks of the electronic memory; and a transfer block size estimator configured to select a transfer block size for the current transfer block based on previous DMA transfers of compressed data, the selected transfer block size being generally different from the storage block size.

Claims

1. An image processing device comprising:

a marking engine;

an image compressor configured to compress image data;

an image decompressor configured to decompress image data previously compressed by the image compressor;

an electronic memory organized as storage blocks each having a storage block size;

a direct memory access (DMA) engine configured to transfer compressed image data from the image compressor into the electronic memory and to transfer compressed image data from the electronic memory to the image decompressor;

a central processing unit (CPU) configured to coordinate operations of at least the marking engine and DMA engine to cause the marking engine to generate markings in accordance with selected image data input to the image compressor; and

a transfer block size estimator configured to adjust a transfer block size used in transfer of compressed image data from the image compressor into the electronic memory based on analysis of previous transfers of compressed image data from the image compressor into the electronic memory, the DMA engine being further configured to transfer a unit of compressed image data having the transfer block size from the image compressor into the electronic memory without intervention of the CPU.

2. The image processing device as set forth in claim 1, wherein the selected transfer block size defines a transfer block size for a single DMA transfer operation.

3. The image processing device as set forth in claim 1, wherein the transfer block size estimator is configured to select the transfer block size as N storage blocks where N is an integer greater than or equal to one, and the DMA engine is configured to transfer a unit of compressed image data having the transfer block size from the image compressor into the electronic memory via N DMA transfer operations using DMA chaining.

4. The image processing device as set forth in claim 1, wherein:

the image processing device is configured to perform jobs; and

the transfer block size estimator is configured to adjust the transfer block size used in transfer of compressed image data from the image compressor into the electronic memory after an interval defined by performance of a selected number of jobs based on analysis of transfers of compressed image data from the image compressor into the electronic memory occurring over the course of performance of the selected number of jobs.

5. The image processing device as set forth in claim 1, wherein the transfer block size estimator is configured to adjust the transfer block size based on cyclical temporal history information pertaining to previous transfers of compressed image data from the image compressor into the electronic memory.

6. The image processing device as set forth in claim 1, wherein the transfer block size estimator is configured to occasionally adjust the transfer block size used in transfer of compressed image data from the image compressor into the electronic memory based on a ratio of (i) compressed scan lines of image data and (ii) quantity of storage blocks of the electronic memory consumed by said compressed scan lines.

7. The image processing device as set forth in claim 1, further comprising:

an optical scanner configured to generate image data for input to the image compressor.

8. The image processing device as set forth in claim 7, wherein the image processing device is a multi-function device (MFD) that provides at least photocopying functionality in conjunction with the optical scanner and the marking engine and printing functionality in conjunction with the marking engine.

9. The image processing device as set forth in claim 7, wherein the CPU is disposed in a first facsimile machine, the marking engine is disposed in a second facsimile machine operatively connected with the first facsimile machine, and the CPU coordinates operation of the marking engine by operatively communicating with the second facsimile machine.

10. The image processing device as set forth in claim 7, wherein the image processing device is a multi-function device (MFD) that provides scan-to-export functionality in conjunction with the optical scanner.

11. A compression and storage device comprising:

a compressor configured to compress data;

a central processing unit (CPU) configured to control storage of the compressed data and to perform at least one additional task;

an electronic memory organized as storage blocks each having a storage block size;

a direct memory access (DMA) engine configured to operate autonomously from the CPU to transfer a current transfer block of compressed data into one or more storage blocks of the electronic memory; and

a transfer block size estimator configured to select a transfer block size for the current transfer block based on previous DMA transfers of compressed data, the selected transfer block size being generally different from the storage block size.

12. The compression and storage device as set forth in claim 11, wherein the DMA engine configuration includes a plurality of independent DMA channels and a transfer block size for each DMA channel.

13. The compression and storage device as set forth in claim 11, wherein the transfer block size estimator is configured to select the transfer block size as N storage blocks where N is an integer greater than or equal to one, and the DMA engine is configured to transfer the current transfer block of compressed data into N storage blocks of the electronic memory using DMA chaining.

14. The compression and storage device as set forth in claim 11, wherein the DMA engine is configured to interrupt the CPU after transfer of the current transfer block is complete.

15. The compression and storage device as set forth in claim 11, wherein the transfer block size estimator operates on a per-image or per-file basis, and is configured to select the transfer block size for the current transfer block based on an analysis of previous DMA transfers of compressed data for the image or file currently being transferred.

16. The compression and storage device as set forth in claim 15, wherein for an image transfer, the analysis includes determining a ratio of:

(i) number of scan lines in the transferred portion of the image currently being transferred and

(ii) storage blocks of memory consumed by the transferred portion of the image currently being transferred.

17. The compression and storage device as set forth in claim 11, wherein the transfer block size estimator is configured to select the transfer block size for the current transfer block based at least in part on an analysis of previous DMA transfers of compressed data for one or more previously transferred images or files.

18. The compression and storage device as set forth in claim 17, wherein the transfer block size estimator is configured to:

estimate a typical compression ratio achieved for said one or more previously transferred images or files, and

estimate the transfer block size for the current transfer block based on the typical compression ratio and an uncompressed size of the image or file currently being transferred.

19. The compression and storage device as set forth in claim 11, wherein the at least one additional task performed by the CPU includes causing the DMA engine to retrieve compressed images from the electronic memory, decompressing or causing decompression of the retrieved images, and causing marking of a sheet in accordance with the retrieved and decompressed images.

20. The compression and storage device as set forth in claim 11, wherein the at least one additional task performed by the CPU includes causing the DMA engine to retrieve compressed images or files from the electronic memory and causing wireless transmission of the retrieved compressed images or files.

21. The compression and storage device as set forth in claim 11, wherein the at least one additional task performed by the CPU includes causing an optical scanner to generate image data that is input to the compressor.

22. An image processing device comprising:

a marking engine;

an image compressor configured to compress image data;

an image decompressor configured to decompress image data previously compressed by the image compressor;

an electronic memory;

a direct memory access (DMA) engine configured to transfer compressed image data from the image compressor into the electronic memory and to transfer compressed image data from the electronic memory to the image decompressor;

a central processing unit (CPU) configured to coordinate operations of at least the marking engine and DMA engine to cause the marking engine to generate markings in accordance with selected image data input to the image compressor; and

a transfer block size estimator configured to adjust a transfer block size for autonomous transfer of compressed image data from the image compressor into the electronic memory based on analysis of previous transfers of compressed image data from the image compressor into the electronic memory.

23. The image processing device as set forth in claim 22, wherein the transfer block size estimator is configured to select the transfer block size as N storage blocks where N is an integer greater than or equal to one, and the DMA engine is configured to transfer a unit of compressed image data having the transfer block size from the image compressor into the electronic memory using DMA chaining.

24. The image processing device as set forth in claim 22, wherein the transfer block size estimator is configured to adjust the transfer block size less often than after every autonomous transfer.