Low-power USB superspeed device with 8-bit payload and 9-bit frame NRZI encoding for replacing 8/10-bit encoding
First Claim
1. A low-power Universal-Serial-Bus (USB) device comprising:
- a transmit pair for sending data to a host;
a receive pair for receiving data from the host;
a low-power physical layer that comprises;
a set of two pairs of differential serial buses, a first pair bus with a first pin carry+signal and a second pin carry−
signal, and a second pair differential serial bus with a first pin carry+signal and a second pin carry−
signal, wherein the set of two pairs of differential serial buses comprises the receive pair and the transmit pair;
a driver for driving the transmit pair with a transmit data stream;
a bit clock for clocking bits of the transmit data stream;
a parallel-to-serial converter, clocked by the bit clock, for converting data bytes for transmission to serial data for transmission by the driver;
a receiver for detecting signal transitions on the receive pair;
a receive clock recovery circuit, coupled to the receiver, for generating a received bit clock from the signal transitions detected by the receiver;
a sync pattern detector for detecting sync patterns received by the receiver;
a serial-to-parallel converter, clocked by the received bit clock, for converting the extracted data stream to received data bytes;
an elastic buffer for storing the received data bytes;
a low-power link layer, coupled to the low-power physical layer, for generating and processing link control words for controlling link power and for link training; and
a scaled-down protocol layer for pointing to headers and payloads in a memory buffer for transfer to the low-power link layer;
a flash memory for storing data in non-volatile memory; and
a RAM buffer coupled to the scaled-down protocol layer, for storing output parallel words read from the flash memory by a flash interface, and for storing input parallel words before writing to the flash memory by the flash interface; and
a microcontroller coupled to receive addresses, commands, and data from the scaled-down protocol layer, for generating flash commands for accessing the flash memory, the microcontroller generating a not-yet signal that is transmitted to the host over the transmit pair when the RAM buffer does not yet contain requested data that is waiting to be read from the flash memory,whereby the not-yet signal is transmitted over the transmit pair when the requested data is waiting to be read from the flash memory.
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Abstract
A Low-power flash-memory device uses a modified Universal-Serial-Bus (USB) 3.0 Protocol to reduce power consumption. The bit clock is slowed to reduce power and the need for pre-emphasis when USB cable lengths are short in applications. Data efficiency is improved by eliminating the 8/10-bit encoder and instead encoding sync and framing bytes as 9-bit symbols. Data bytes are expanded by bit stuffing only when a series of six ones occurs in the data. Header and payload data is transmitted as nearly 8-bits per data byte while framing is 9-bits per symbol, much less than the standard 10 bits per byte. Low-power link layers, physical layers, and scaled-down protocol layers are used. A card reader converter hub allows USB hosts to access low-power USB devices. Only one flash device is accessed, reducing power compared with standard USB broadcasting to multiple devices.
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Citations
22 Claims
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1. A low-power Universal-Serial-Bus (USB) device comprising:
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a transmit pair for sending data to a host; a receive pair for receiving data from the host; a low-power physical layer that comprises; a set of two pairs of differential serial buses, a first pair bus with a first pin carry+signal and a second pin carry−
signal, and a second pair differential serial bus with a first pin carry+signal and a second pin carry−
signal, wherein the set of two pairs of differential serial buses comprises the receive pair and the transmit pair;a driver for driving the transmit pair with a transmit data stream; a bit clock for clocking bits of the transmit data stream; a parallel-to-serial converter, clocked by the bit clock, for converting data bytes for transmission to serial data for transmission by the driver; a receiver for detecting signal transitions on the receive pair; a receive clock recovery circuit, coupled to the receiver, for generating a received bit clock from the signal transitions detected by the receiver; a sync pattern detector for detecting sync patterns received by the receiver; a serial-to-parallel converter, clocked by the received bit clock, for converting the extracted data stream to received data bytes; an elastic buffer for storing the received data bytes; a low-power link layer, coupled to the low-power physical layer, for generating and processing link control words for controlling link power and for link training; and a scaled-down protocol layer for pointing to headers and payloads in a memory buffer for transfer to the low-power link layer; a flash memory for storing data in non-volatile memory; and a RAM buffer coupled to the scaled-down protocol layer, for storing output parallel words read from the flash memory by a flash interface, and for storing input parallel words before writing to the flash memory by the flash interface; and a microcontroller coupled to receive addresses, commands, and data from the scaled-down protocol layer, for generating flash commands for accessing the flash memory, the microcontroller generating a not-yet signal that is transmitted to the host over the transmit pair when the RAM buffer does not yet contain requested data that is waiting to be read from the flash memory, whereby the not-yet signal is transmitted over the transmit pair when the requested data is waiting to be read from the flash memory. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A Universal-Serial-Bus (USB) low-power host comprising:
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a host processor for executing instructions; a main memory for storing data; an Input-Output processor, coupled to the host processor, for accessing peripherals on a peripheral bus; a host low-power USB port connected to a first pair and to a second pair of lines; a host simplified low-power USB controller for accessing a low-power USB device;
wherein the host simplified low-power USB controller comprises;a host low-power physical layer coupled to the host low-power USB port; a host low-power link layer coupled to the host low-power physical layer; a host scaled-down protocol layer coupled to the host low-power link layer; wherein the USB low-power host suspends sending serial packets to a low-power USB flash device during a low-power suspend mode, the USB low-power host not polling the low-power USB device in response to a not-yet signal sent by the low-power USB flash device to reduce power consumption of the USB low-power host. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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20. A low-power card reader comprising:
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a Universal-Serial-Bus (USB) port for connecting to a host over a receive pair and a transmit pair of lines; wherein the receive pair and the transmit pair together comprise a set of two pairs of differential serial buses, a first pair bus with a first pin carry+signal and a second pin carry−
signal, and a second pair differential serial bus with a first pin carry+signal and a second pin carry−
signal;a physical layer coupled to the USB port to receive a received data stream from the receive pair, and to transmit a transmit data stream to the transmit pair; wherein the physical layer further comprises; an 8/10-bit encoder/decoder for converting 10-bit symbols from the received data stream into 8-bit received data bytes, and for converting 8-bit transmit data bytes into 10-bit transmit symbols to form the transmit data stream; a descrambler for descrambling the 8-bit received data bytes and for scrambling the 8-bit transmit data bytes; a cyclical-redundancy-check (CRC) generator/checker for generating a CRC for the 8-bit transmit data bytes, and for checking a CRC for the 8-bit received data bytes; a link layer, coupled to the physical layer, for processing link control words received from the host over the receive pair, for controlling link power and link training; a command buffer, coupled to the link layer, for storing commands and data passed through the link layer; a low-power link layer, coupled to the command buffer; a low-power physical layer, coupled to the low-power link layer, the low-power physical layer comprising; a sync pattern generator for generating 9-bit symbols representing framing patterns; a bit stuffer for inserting a stuffed bit causing a signal transition on a flash pair of lines, the bit stuffer inserting the stuffed bit into a flash data stream after a predetermined number of bits that do not cause the signal transition occur in a sequence; a NRZI encoder, receiving the flash data stream and the stuffed bit from the bit stuffer, and receiving the 9-bit symbols from the sync pattern generator, for generating flash data in a Not-Return-to-Zero-Inverse (NRZI) format; a RAM buffer coupled to a scaled-down protocol layer, for storing output parallel words read from a flash memory by a flash interface, and for storing input parallel words before writing to the flash memory by the flash interface; and a microcontroller coupled to receive addresses, commands, and data from the scaled-down protocol layer, for generating flash commands for accessing the flash memory, the microcontroller generating a not-yet signal that is transmitted to the host over the transmit pair when the RAM buffer does not yet contain requested data that is waiting to be read from the flash memory, whereby the not-yet signal is transmitted over the transmit pair when the requested data is waiting to be read from the flash memory. - View Dependent Claims (21, 22)
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Specification