Controlling auxiliary power to logic devices

• US 8,166,330 B2
• Filed: 12/06/2007
• Issued: 04/24/2012
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Mizrachi, Shay, Pickholz, Arik
• Primary Examiner(s): WANG, ALBERT C
• Application Number:
  US11/951,759
• Publication Number:
  US 20090150702A1
• Time in Patent Office: 1,601 Days
• Field of Search: 713/330, 713/324, 710/16
• US Class Current: 713/330
• CPC Class Codes: G06F 1/30 Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations for resetting only G06F1/24
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode

Abstract

Various example implementations are disclosed. According to one example implementation, a system may include multiple logic devices, a power input, and a logic controller. The logic devices may each be configured to assert a request for auxiliary power to a logic controller. The power input may be configured to provide the auxiliary power to one or more of the logic devices. The logic controller may be configured to poll the logic devices by polling less than all of the logic devices at a time to determine whether the logic devices assert the request for the auxiliary power.

Claims

1. A system comprising:

multiple logic devices, each of the logic devices being configured to assert a request for auxiliary power to a logic controller;

a power input configured to provide the auxiliary power to the logic devices, the auxiliary power being insufficient to provide power to all of the logic devices; and

a logic controller configured to poll the logic devices by;

allowing the power input to provide the auxiliary power to less then all of the logic devices at a time; and

if the polled logic devices do not assert the request for auxiliary power while the auxiliary power is provided, cease allowing the power input to provide the auxiliary power to the polled logic devices which did not assert the request.

2. The system of claim 1 wherein the power input is configured to provide main power to all of the logic devices instead of the auxiliary power in response to main power becoming available to the power input, the main power being sufficient to provide power to all of the logic devices.

3. The system of claim 1 wherein the logic controller is configured to continue to allow the power input to provide the auxiliary power to a first logic device which asserts the request for the auxiliary power while polling other logic devices.

4. The system of claim 1 wherein the logic devices are configured to instruct the power input to switch from the auxiliary power to a main power in response to the logic devices receiving a wakeup packet while the logic devices are powered by the auxiliary power.

5. The system of claim 1 wherein the logic controller is configured to poll the logic devices by polling less then all of the logic devices at a time to determine whether the logic devices assert the request for the auxiliary power by:

enabling the power input to provide the auxiliary power to a first polled logic device;

continuing to allow the power input to provide the auxiliary power to the first polled logic device in response to receiving the request signal from the first polled logic device; and

disabling the power input from providing the auxiliary power to the first polled logic device, and polling a second logic device, in response to either receiving a no-request signal from the first polled logic device or a timer expiring without receiving the request from the first polled logic device.

6. The system of claim 1 wherein the logic controller is configured to poll the logic devices a second time in response to a timeout occurring after a first polling.

7. The system of claim 1 further comprising:

multiple enabling nodes, each of the enabling nodes coupling the power input to one of the logic devices,

wherein the logic controller is configured to;

allow the power input to provide the auxiliary power to a first polled logic device by enabling the corresponding enabling node;

continue to allow the power input to provide the auxiliary power to the first polled logic device by leaving the corresponding enabling node in an enabled state; and

disabling the power input from providing the auxiliary power to the first polled logic device by disabling the corresponding enabling node.

8. The system of claim 1 wherein the logic controller is configured to:

determine a number of the logic devices for which the auxiliary power is able to provide a threshold power level; and

poll the less than all of the logic devices at a time by polling the logic devices in groups based on the determined number of logic devices.

9. The system of claim 1 wherein the logic controller is configured to poll the logic devices according to a predetermined sequence.

10. The system of claim 1 further comprising:

multiple dedicated request pins, each dedicated request pin coupling one of the logic devices to the logic controller,

wherein each of the logic devices is configured to assert the request for auxiliary power using its dedicated request pin, and

wherein the logic controller is configured to poll the logic devices using dedicated request pins.

11. The system of claim 1 wherein each of the logic devices is configured to assert the request for auxiliary power in response to the power input transitioning from no power to the auxiliary power.

12. The system of claim 1, wherein the power input is configured to provide, to the logic devices, main power sufficient to power all of the logic devices and, when the main power is unavailable, the auxiliary power, the auxiliary power being insufficient to provide power to all of the logic devices.

13. A logic controller comprising:

multiple pins configured to receive requests for auxiliary power from multiple logic devices, the auxiliary power being insufficient to provide power to all of the logic devices; and

a logic circuit configured to poll the multiple logic devices by;

enabling the auxiliary power to less than all of the logic devices at a time; and

if the polled logic devices do not assert requests for auxiliary power while the auxiliary power is enabled, disabling the auxiliary power to the polled logic devices which did not assert the requests.

14. The logic controller of claim 13, wherein the logic circuit is further configured to instruct the power input to switch from providing a main power to the logic devices to providing the auxiliary power to the logic devices based on the main power falling below a threshold.

15. The logic controller of claim 13, wherein the logic circuit is configured to continue to enable the auxiliary power to a first logic device which asserts the request for the auxiliary power while polling other logic devices.

16. The logic controller of claim 13, wherein the logic circuit is configured to poll the logic devices by polling less then all of the logic devices at a time to determine whether the logic devices assert the request for the auxiliary power by:

enabling the auxiliary power to a first polled logic device;

continuing to enable the auxiliary power to the first polled logic device in response to receiving the request signal from the first polled logic device; and

disabling the auxiliary power to the first polled logic device, and polling a second logic device, in response to either receiving a no-request signal from the first polled logic device or a timer expiring without receiving the request from the first polled logic device.

17. The logic controller of claim 13, wherein the logic circuit is configured to poll the logic devices a second time in response to a timeout occurring after a first polling.

18. The logic controller of claim 13, wherein the logic circuit is configured to:

determine a number of the logic devices for which the auxiliary power is able to provide a threshold power level; and

poll the less than all of the logic devices at a time by polling the logic devices in groups based on the determined number of logic devices.

19. The logic controller of claim 13, wherein the logic circuit is configured to poll the logic devices according to a predetermined sequence.