Information processing apparatus, information processing method, and computer program

• US 8,166,339 B2
• Filed: 03/11/2009
• Issued: 04/24/2012
• Est. Priority Date: 04/21/2008
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Kyusojin, Hiroshi
• Primary Examiner(s): Baderman, Scott
• Assistant Examiner(s): KO, CHAE M
• Application Number:
  US12/401,684
• Publication Number:
  US 20090265500A1
• Time in Patent Office: 1,140 Days
• Field of Search: 714/42, 714/4.2, 714/4.11, 714/6.3
• US Class Current: 714/6.3
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 2212/2542 Non-uniform memory access [NUMA] architecture

Abstract

An information processing apparatus including a plurality of nodes, each node connecting at least a memory and a processor to a system bus; an interconnection bus that interconnects the nodes; a device that is connected to a system bus on any of the plurality of nodes and performs data processing; and a memory selecting unit that selects a memory connected to the system bus to which the device is connected as a memory to be accessed by the device.

Claims

1. An information processing apparatus, comprising:

a plurality of nodes, the nodes comprising memories and processors connected to corresponding system buses;

an interconnection bus configured to interconnect the nodes;

a device configured to perform data processing, the device being connected to a first one of the system buses; and

a memory selecting unit configured to;

select a first one of the memories, the first memory being associated with the first system bus;

determine whether the first memory is accessible to the device;

select a second one of the memories, when the first memory fails to be accessible to the device, wherein the second memory is associated with a second system bus different from the first system bus;

determine whether cache coherency is maintained between the nodes associated with the first and second system buses;

invalidate a cache corresponding to the node associated with the second system bus, when cache coherency fails to be maintained; and

enable the device to access the second memory associated with the second system bus.

2. The information processing apparatus of claim 1, wherein the memory selecting unit, is further configured to terminate the data processing performed by the device, when the first memory fails to be accessible to the device.

3. The information processing apparatus according to of claim 1, wherein the memory selecting unit is further configured to repeat the selection of the first memory, when the first memory fails to be accessible to the device.

4. The information processing apparatus of claim 1, further comprising a processor selecting unit configured to select a first processor connected to the first system bus, the first processor being configured to execute a device driver corresponding to the device.

5. The information processing apparatus of claim 4, wherein the first processor is configured to execute an application using the device.

6. The information processing apparatus of claim 4, wherein:

the device driver comprises a main processing performing portion configured to perform main data processing and an interrupt processing performing portion configured to perform interrupt processing; and

the first processor is configured to execute the main processing performing portion, and a second processor that is different from the first processor is configured to execute the interrupt processing performing portion.

7. The information processing apparatus of claim 6, wherein the interrupt processing performing is configured to select the second processor using one or more selecting schemes, the selecting schemes comprising at least one of selecting a processor connected to the first system bus, selecting a processor based on a corresponding processor load, or selecting a processor using the round-robin scheme.

8. The information processing apparatus of claim 6, wherein:

the device is configured to perform communication processing; and

the main processing performing portion is executed by the device to perform at least one of data sending completion processing, data reception completion processing or error processing.

9. An information processing method, comprising:

identifying a plurality of nodes and a device configured to perform data processing, the nodes comprising memories and processors in connection with corresponding system buses, and the device being connected to a first one of the system buses;

selecting a first one of the memories, the first memory being associated with the first system bus;

determining whether the first memory is accessible to the device;

selecting a second one of the memories, when the first memory fails to be accessible to the device, wherein the second memory is associated with a second system bus different from the first system bus;

determining whether cache coherency is maintained between the nodes associated with the first and second system buses;

invalidating a cache associated with the second system bus, when cache coherency fails to be maintained; and

enabling the device to access the second memory associated with the second system bus.

10. A non-transitory, computer-readable storage medium storing a program that, when executed by a processor, causes the processor to perform a method for information processing, comprising:

identifying a plurality of nodes and a device configured to perform data processing, the nodes comprising memories and processors in connection with corresponding system buses, and the device being connected to a first one of the system buses;

selecting a first one of the memories, the first memory being associated with the first system bus;

determining whether the first memory is accessible to the device; and

selecting a second one of the memories, when the first memory fails to be accessible to the device, wherein the second memory is not associated with a second system bus different from the first system bus;

determining whether cache coherency is maintained between the nodes associated with the first and second system buses;

invalidating a cache associated with the second system bus, when cache coherency fails to be maintained; and

enabling the device to access the second memory associated with the second system bus.