Tracing and reporting registers removed during synthesis

• US 8,166,427 B1
• Filed: 03/07/2008
• Issued: 04/24/2012
• Est. Priority Date: 03/09/2007
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Van Antwerpen, Babette, Hutton, Michael D., Leaver, Andrew, Pathak, Swatiben Ruturaj
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US12/044,926
• Time in Patent Office: 1,509 Days
• Field of Search: 716/1, 716/2, 716/4, 716/5, 716/18, 716/106, 716/107.136, 716/104, 714/30, 714/724
• US Class Current: 716/104
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]

Abstract

Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of registers and determines why the registers were removed. This information is then provided in an efficient manner for design debugging purposes.

Claims

1. A system comprising a processor, the processor configured to:

select a first component of an integrated circuit from a model of the integrated circuit during a synthesis stage;

identify the first component as stuck during the synthesis stage and identify a second component as a blame component corresponding to the stuck first component;

generate a message indicating that the first component is stuck and that the second component is the blame component corresponding to the stuck first component; and

provide the message for rendering on a display.

2. The system of claim 1, wherein the message comprises a stuck value of the first component.

3. The system of claim 1, wherein the first component comprises a register.

4. The system of claim 1, wherein the first component comprises a plurality of registers.

5. The system of claim 1, wherein a format of the message is selected from the group consisting of a schematic, a layout, and a text source file.

6. The system of claim 1, wherein the first component is removed from the integrated circuit during the synthesis stage.

7. The system of claim 1, wherein the display presents the message in a graphical user interface.

8. The system of claim 1, wherein the message is printed.

9. A system comprising:

a memory, the memory configured to store a list of descriptions of components of an integrated circuit during a synthesis stage; and

a processor, the processor configured to;

identify a first component of the integrated circuit as stuck during the synthesis stage and identify a second component as a blame component corresponding to the stuck first component;

generate a description indicating that the first component is stuck and that the second component is the blame component corresponding to the stuck first component; and

add the description to the list of descriptions.

10. The system of claim 9, wherein the description comprises a stuck value of the first component.

11. The system of claim 9, wherein the first component comprises a register.

12. The system of claim 9, wherein the first component comprises a plurality of registers.

13. The system of claim 9, wherein a format of the description is selected from the group consisting of a schematic, a layout, and a text source file.

14. The system of claim 9, wherein the processor is further configured to identify one of the descriptions in the list of descriptions as corresponding to a root-cause circuit.

15. The system of claim 9, wherein the list of descriptions is displayed using a graphical user interface.

16. The system of claim 9, wherein the list of descriptions is printed.

17. A method of generating circuit synthesis information, the method comprising:

applying an input signal to a first circuit of an integrated circuit and measuring a corresponding output signal of the first circuit;

determining that the corresponding output signal remains constant as the input signal is varied; and

identifying, using a processor, a second circuit as a blame circuit corresponding to the first circuit, wherein the second circuit has an output port that is coupled to an input port of the first circuit;

generating a message indicating that the second circuit is the blame circuit corresponding to the first circuit; and

providing the message for rendering on a display.

18. The method of claim 17, further comprising:

displaying a description of a third circuit, wherein the description indicates that the third circuit is a victim of the first circuit.

19. The method of claim 18, wherein the first circuit is removed from the integrated circuit during a circuit synthesis.

20. The method of claim 18, wherein the first, second, and third circuits are each removed from the integrated circuit during a circuit synthesis.

21. The method of claim 20, further comprising displaying the identity of the second circuit, and an identity of the first circuit and the third circuit.

22. The method of claim 18, wherein the first circuit is a logic gate.

23. The method of claim 18, wherein a supply voltage is coupled to an input port of the first circuit.

24. The method of claim 18, wherein the first circuit is a register.

25. The method of claim 18, wherein the first circuit is a synchronous circuit.

26. The method of claim 17, wherein an identity of the first circuit is listed in tabular data-structure to associate the first circuit with the second and third circuits.

27. The method of claim 26, wherein a post-processing operation traverses the tabular data-structure to determine an initial cause for why the output signal remains constant as the input signal is varied of the first circuit.