Timing operations in an IC with configurable circuits

• US 8,166,435 B2
• Filed: 06/26/2008
• Issued: 04/24/2012
• Est. Priority Date: 06/26/2008
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Tabula Incorporated
• Inventors: Teig, Steven, Caldwell, Andrew
• Primary Examiner(s): Whitmore, Stacy
• Assistant Examiner(s): DIMYAN, MAGID Y
• Application Number:
  US12/215,697
• Publication Number:
  US 20090327987A1
• Time in Patent Office: 1,398 Days
• Field of Search: 716/116, 716/117, 716/122, 716/126
• US Class Current: 716/116
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: H03K 19/1731 Optimisation thereof
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources

Abstract

Some embodiments provide a method that identifies a first physical design solution for positioning several configurable operations on several reconfigurable circuits of an integrated circuit (IC). The method identifies a second physical design solution for positioning the configurable operations on the configurable circuits. One of the identified physical design solutions has one reconfigurable circuit perform a particular configurable operation in at least two reconfiguration cycles while the other identified solution does not have one reconfigurable circuit perform the particular configurable operation in two reconfiguration cycles. The method costs the first and second physical design solutions. The method selects one of the two physical design solutions based on the costs.

Claims

1. A method of optimizing a physical design of an integrated circuit (IC), the IC comprising a plurality of reconfigurable circuits for configurably performing a plurality of operations, the method comprising:

identifying, using a computer, a first physical design solution for assigning a plurality of configurable operations to the plurality of reconfigurable circuits of the IC;

modifying the first physical design solution to produce a second physical design solution by selecting a reconfigurable circuit that performs a particular configurable operation in a particular reconfiguration cycle in the first physical design solution and assigning said reconfigurable circuit to perform the particular configurable operation in at least two consecutive reconfiguration cycles in the second physical design solution;

computing a cost for assigning said reconfigurable circuit to perform the particular configurable operation in at least two consecutive reconfiguration cycles in the second physical design solution; and

based on the computed cost, selecting between the first and second physical design solutions.

2. The method of claim 1, wherein the second physical design solution uses a storage element to facilitate having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles.

3. The method of claim 2, wherein the storage element is a latch.

4. The method of claim 1, wherein computing the cost comprises penalizing the second physical design solution for having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles.

5. The method of claim 1 further comprising computing a cost for performing the particular configurable operation in the particular reconfiguration cycle in the first physical design solution, wherein each computed cost comprises an associated timing cost, wherein having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles improves the associated timing cost of the second physical design solution relative to the associated timing cost of the first physical design solution.

6. The method of claim 1, wherein the plurality of reconfigurable circuits comprise reconfigurable logic circuits.

7. The method of claim 1, wherein the physical design solutions comprise placement solutions.

8. The method of claim 1, wherein the plurality of reconfigurable circuits comprise reconfigurable interconnect circuits.

9. The method of claim 1, wherein the physical design solutions comprise routing solutions.

10. The method of claim 1, wherein assigning the plurality of configurable operations to the plurality of reconfigurable circuits comprises assigning the particular configurable operation to said reconfigurable circuit in the particular reconfiguration cycle.

11. The method of claim 10, wherein a configuration data set specifies the particular configurable operation of said configurable circuit in the particular reconfiguration cycle in the first physical design solution and in at least two consecutive reconfiguration cycles in the second physical design solution.

12. The method of claim 1 further comprising computing a cost for performing the particular configurable operation in the particular reconfiguration cycle in the first physical design solution, wherein each computed cost comprises an associated area cost, wherein having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles worsens the associated area cost of the second physical design solution relative to the associated area cost of the first physical design solution.

13. The method of claim 1, wherein computing the cost for assigning the reconfigurable circuit to perform the particular configurable operation in at least two reconfiguration cycles in the second physical design solution comprises computing a differential cost for modifying the first physical design solution to produce the second physical design solution, wherein selecting between the first and second physical design solutions is based on the differential cost.

14. The method of claim 1 further comprising computing a cost for performing the particular configurable operation in the particular reconfiguration cycle in the first physical design solution, wherein computing the costs comprises computing a total cost for each physical design solution, wherein selecting between the first and second physical design solutions comparing the total costs.

15. A non-transitory machine readable medium storing a program for optimizing a physical design of an integrated circuit (IC), the IC comprising a plurality of reconfigurable circuits for configurably performing a plurality of operations, the program executable by a processor, the program comprising sets of instructions for:

identifying a first physical design solution for assigning a plurality of configurable operations to the plurality of reconfigurable circuits of the IC;

modifying the first physical design solution to produce a second physical design solution by selecting a reconfigurable circuit that performs a particular configurable operation in a particular reconfiguration cycle in the first physical design solution and assigning said reconfigurable circuit to perform the particular configurable operation in at least two consecutive reconfiguration cycles in the second physical design solution;

computing a cost for assigning said reconfigurable circuit to perform the particular configurable operation in at least two consecutive reconfiguration cycles in the second physical design solution; and

selecting between the first and second physical design solutions based on the computed cost.

16. The non-transitory machine readable medium of claim 15, the program further comprising a set of instructions for inserting a storage element in the second physical design solution to facilitate having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles.

17. The non-transitory machine readable medium of claim 16, wherein the storage element is a latch.

18. The non-transitory machine readable medium of claim 15, wherein the set of instructions for computing the cost for assigning the reconfigurable circuit to perform the particular configurable operation in at least two consecutive reconfiguration cycles comprises a set of instructions for assessing a penalty for performing the particular configurable operation in at least two consecutive reconfiguration cycles instead of in one reconfiguration cycle.

19. The non-transitory machine readable medium of claim 15, the program further comprising a set of instructions for computing a cost for performing the particular configurable operation in the particular reconfiguration cycle in the first physical design solution, wherein each computed cost comprises an associated timing cost, wherein having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles improves the associated timing cost of the second physical design solution relative to the associated timing cost of the first physical design solution.

20. The non-transitory machine readable medium of claim 15, the program further comprising a set of instructions for computing a cost for performing the particular configurable operation in the particular reconfiguration cycle in the first physical design solution, wherein each computed cost comprises an associated area cost, wherein having the reconfigurable circuit perform the particular configurable operation in at least two consecutive reconfiguration cycles worsens the associated area cost of the second physical design solution relative to the associated area cost of the first physical design solution.

21. The non-transitory machine readable medium of claim 15, wherein the set of instructions for computing the cost for assigning the reconfigurable circuit to perform the particular configurable operation in at least two reconfiguration cycles in the second physical design solution comprises a set of instructions for computing a differential cost for modifying the first physical design solution to produce the second physical design solution, wherein the set of instructions for selecting between the first and second physical design solutions is based on the differential cost.

22. The non-transitory machine readable medium of claim 15, the program further comprising a set of instructions for computing a cost for the first physical design solution of performing the particular configurable operation in the particular reconfiguration cycle, wherein the set of instructions for computing the cost comprises a set of instructions for computing a total cost for each physical design solution, wherein the set of instructions for selecting between the first and second physical design solutions comprises a set of instructions for comparing the total costs.