Method of manufacturing a printed circuit board

• US 8,166,650 B2
• Filed: 05/30/2008
• Issued: 05/01/2012
• Est. Priority Date: 05/30/2008
• Status: Active Grant

• Current Assignee: GM Global Technology Operations Incorporated (Motors Liquidation Co. GUC Trust), Steering Solutions IP Holding Corporation (Nexteer Automotive Group Ltd.)
• Original Assignee: Steering Solutions IP Holding Corporation (Nexteer Automotive Group Ltd.)
• Inventors: Thomas, Wayne Bernard
• Primary Examiner(s): ARBES, CARL J
• Application Number:
  US12/129,938
• Publication Number:
  US 20090294165A1
• Time in Patent Office: 1,432 Days
• Field of Search: 298/32, 298/40, 298/52, 298/48, 228/180.22, 438/629
• US Class Current: 29/852
• CPC Class Codes: H05K 1/0206 by printed thermal vias
• CPC Class Codes: H05K 1/0207 using internal conductor planes parallel to the surface for thermal conduction, e.g. power planes
• CPC Class Codes: H05K 2201/09309 Core having two or more power planes; Capacitive laminate of two power planes
• CPC Class Codes: H05K 2201/0959 Plated through-holes or plated blind vias filled with insulating material
• CPC Class Codes: H05K 2201/10166 Transistor
• CPC Class Codes: H05K 3/0094 Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
• CPC Class Codes: H05K 3/282 for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
• CPC Class Codes: H05K 3/3452 Solder masks
• CPC Class Codes: H05K 3/429 Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers
• CPC Class Codes: Y10T 29/49144 by metal fusion
• CPC Class Codes: Y10T 29/49165 by forming conductive walled aperture in base

Abstract

A method of manufacturing a printed circuit board (PCB) includes of disposing thermal transfer vias and electrical vias through the PCB. The method further includes filling holes of the vias with a solder mask. The thermal transfer vias are filled to about 70% of capacity while the electrical vias are completely filled. Once filled, surfaces of the PCB are coated with an organic solderability preservative.

Claims

1. A method of manufacturing a printed circuit board (PCB) having at least one conductive layer and at least one non-conductive layer and forming a first surface and a second surface, said method comprising:

disposing at least one via through the PCB to connect the surfaces wherein the at least one via includes a metallic portion having a pair of ends and defining a hole;

filling the hole of the at least one via with a solder mask to a certain level between the ends; and

coating at least a portion of one of the surfaces of the PCB with an organic solderability preservative (OSP).

2. A method as set forth in claim 1 wherein the at least one via is further defined as a plurality of vias including at least one thermal transfer via for conduction of heat between the surfaces and at least one electrical via for conduction of electrical current between the surfaces.

3. A method as set forth in claim 2 wherein said step of filling the hole of the at least one via with a solder mask is further defined as filling the hole of the at least one electrical via with a solder mask to a level of about 100 percent of the height of the electrical via.

4. A method as set forth in claim 2 wherein said step of filling the hole of the at least one via with a solder mask is further defined as filling the hole of the at least one thermal transfer via with a solder mask to a level between 45 and 95 percent of the height of the thermal transfer via.

5. A method as set forth in claim 4 wherein the level is about 70 percent of the height of the thermal transfer via.

6. A method as set forth in claim 2 wherein said step of filling the hole of the at least one via with a solder mask is further defined as filling the hole of the at least one electrical via with a solder mask to a level of about 100 percent of the height of the electrical via and filling the hole of the at least one thermal transfer via with a solder mask to a level between 45 and 95 percent of the height of the thermal transfer via.

7. A method as set forth in claim 2 further comprising the step of placing a thermal transfer material in thermal communication with the at least one thermal transfer via for transferring heat from the thermal transfer via.

8. A method as set forth in claim 2 further comprising the step of placing a heat sink in thermal communication with the at least one thermal transfer via for transferring heat from the thermal transfer via.

9. A method as set forth in claim 1 wherein said step of coating at least a portion of one the surfaces of the PCB with the OSP is performed in response to said the filling of the hole of the at least one via.

10. A method of manufacturing a printed circuit board (PCB) having a pair of conductive layers and at least one non-conductive layer sandwiched between said conductive layers and wherein said conductive layers define a first surface and a second surface, said method comprising:

disposing at least one electrical via defining a pair of ends and a hole extending between said ends through the layers to electrically connect the conductive layers;

completely filling the hole of the electrical via with a solder mask;

disposing at least one thermal transfer via defining a pair of ends and a hole extending between said ends through the layers to connect the surfaces; and

partially filling the hole of the thermal transfer via with a solder mask.

11. A method as set forth in claim 10 further comprising the step of coating at least a portion of one of the surfaces of the PCB with an organic solderability preservative (OSP).