Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same

• US 8,168,492 B2
• Filed: 04/05/2010
• Issued: 05/01/2012
• Est. Priority Date: 09/19/2003
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Sung-Min, Park, Dong-Gun, Kim, Dong-Won, Kim, Min-Sang, Yun, Eun-jung
• Primary Examiner(s): Smith, Bradley K
• Assistant Examiner(s): Movva, Amar
• Application Number:
  US12/754,128
• Publication Number:
  US 20100221876A1
• Time in Patent Office: 757 Days
• Field of Search: 438/206, 438/212, 257/240, 257/241, 257/244, 257/E21.422
• US Class Current: 438/206
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/105 including field-effect components
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

Claims

1. A method of forming a semiconductor device, comprising:

providing a first transistor in a first region of a semiconductor layer, comprising;

providing a cavity that extends in a vertical direction in the semiconductor layer;

providing a first gate dielectric at a lower portion and inner sidewalls of the cavity;

providing a gate electrode that fills a remaining portion of the cavity, the gate electrode extending in the vertical direction;

providing a source region and a drain region in the semiconductor layer that are arranged at opposite sides of the gate electrode in a horizontal direction; and

providing a lateral channel region of the semiconductor layer at a side of the gate electrode in a lateral direction that extends in the horizontal direction between the source region and the drain region wherein the lateral channel region of the first transistor comprises a first lateral channel region and a second lateral channel region at opposite sides of the gate electrode, each extending in the horizontal direction between the source region and the drain region; and

providing a second transistor in a second region of the semiconductor layer, the second transistor comprising a planar transistor.

2. The method of claim 1 wherein providing the second transistor comprises:

providing a second gate dielectric on the semiconductor layer;

providing a gate electrode on the second gate dielectric; and

providing a first channel region in the semiconductor layer that lies below a gate electrode and not at a lateral side portion of the gate electrode in a lateral direction that extends in the horizontal direction between the source region and the drain region.

3. The method of claim 1 wherein the first region is a memory cell region of the semiconductor device and wherein the second region is a peripheral region of the semiconductor device.

4. The method of claim 1 further comprising providing an isolation region between the first transistor and the second transistor.

5. The method of claim 1 further comprising providing in the first transistor a lower channel region that extends under the gate electrode between the source region and the drain region of the first transistor.

6. The method of claim 1 wherein the semiconductor layer comprises a semiconductor substrate.

7. The method of claim 1 wherein the semiconductor layer is one selected from the group consisting of SOI (silicon-on-insulator), SiGe (silicon germanium), and SGOI (silicon germanium on insulator) layers.

8. The method of claim 1 wherein providing the lateral channel region provides a lateral channel region that is of a height in the vertical direction ranging between about 500 and 2000 Angstroms.

9. The method of claim 1 wherein providing the lateral channel region provides a lateral channel region that is of a height in the vertical direction ranging between about 1000 and 1500 Angstroms.

10. The method of claim 1 wherein providing the lateral channel region provides a lateral channel region of a thickness in the lateral direction less than about 200 Angstroms.

11. The method of claim 1 wherein providing the lateral channel region provides a lateral channel region of a thickness in the lateral direction ranging between about 10 and 150 Angstroms.

12. The method of claim 1 wherein the lateral channel region is of a thickness that is selected as a function of a desired threshold voltage of the first transistor.

13. The method of claim 1 wherein the first gate dielectric is provided between the gate electrode of the first transistor and the source and drain regions and between the gate electrode of the first transistor and the lateral channel region.

14. The method of claim 13 further comprising providing a second dielectric between a gate electrode and a channel region of the second transistor and wherein the second dielectric is of a different thickness than the first dielectric.

15. The method of claim 13 further comprising providing a second dielectric between a gate electrode and a channel region of the second transistor and wherein the second dielectric is of a different material than the first dielectric.

16. The method of claim 1 wherein providing the gate electrode comprises providing a first portion that extends into the semiconductor layer in the vertical direction and a second portion that extends on the semiconductor layer in the horizontal or lateral directions.

17. The method of claim 16 wherein the first portion is formed of a material that is different than the second portion.

18. The method of claim 17 wherein the material of the first portion has a direct effect on a threshold voltage of the first transistor.

19. The method of claim 16 wherein the material of the first portion and the material of the second portion comprise metal and polysilicon respectively.

20. The method of claim 1 wherein a threshold voltage of the first transistor and a threshold voltage of the second transistor are different.

21. The method of claim 1 wherein the gate electrode has a T-shaped cross-section.

22. The method of claim 1 further comprising providing two of the first transistors located adjacent each other in the horizontal direction in the first region, and wherein the two first transistors share a common drain region.

23. The method of claim 1 wherein an outer surface of the lateral channel region opposite the side of the gate electrode is adjacent an insulative region.

24. The method of claim 23 wherein the insulative region comprises a trench isolation region.

25. A method of forming a semiconductor device comprising

defining a first active region and a second active region of a common semiconductor layer by using a first mask layer pattern and a second mask layer pattern, respectively;

etching the first mask layer pattern in the first active region to reduce a width of the first mask layer pattern in a lateral direction by a first distance;

providing a third mask layer on the first active region to at least a level of the first mask layer pattern;

removing the first mask layer pattern in the first active region;

forming a vertical opening in a vertical direction of the semiconductor layer in the first active region using the third mask layer as an etch mask, sidewalls of the vertical opening having adjacent source and drain regions of the first active region in a horizontal direction and having at least one adjacent vertically oriented thin body channel region of the first active region along a sidewall of the vertical opening in the lateral direction;

providing a first gate dielectric on a bottom and the sidewalls of the vertical opening in the first active region;

providing a first gate electrode in a remaining portion of the opening on the gate dielectric in the first active region, to form a first transistor having the vertically oriented thin body channel region in the first active region;

removing the second mask layer to expose a surface of the semiconductor layer in the second active region;

providing a second gate dielectric on the semiconductor layer in the second active region; and

providing a second gate electrode on the second gate dielectric in the second active region, to form a second transistor in the second active region, the second transistor comprising a planar transistor.

26. The method of claim 25 wherein the thickness of the vertically oriented thin body channel region is determined according to the first distance of the reduced width of the first mask layer pattern.

27. The method of claim 25 further comprising forming trenches in the semiconductor layer to define the first active region and the second active region.

28. The method of claim 27 wherein the vertically oriented thin body channel region is formed in the first active region of the semiconductor layer between one of the trenches and the vertical opening.

29. The method of claim 25 further comprising doping the vertically oriented thin body channel region to form a lateral channel region.

30. The method of claim 25 further comprising doping the first active region under the vertical opening to form a lower channel region.

31. The method of claim 25 further comprising doping the source and drain regions of the first active region.

32. The method of claim 25 further comprising forming a buffer layer on the first active region and the second active region between the semiconductor layer and the first mask pattern, and wherein the buffer layer protects an upper surface of the first active region during etching the first mask layer pattern.

33. The method of claim 25 wherein etching the first mask layer pattern further comprises etching the first mask layer pattern in the second active region.

34. The method of claim 25 wherein providing vertical openings comprises providing multiple vertical openings using the second mask layer as an etch mask.

35. The method of claim 25 wherein providing the first gate electrode comprises providing a first portion that extends into the semiconductor layer in the vertical direction and providing a second portion that extends on the semiconductor layer in the horizontal or lateral directions and wherein the first portion is formed of a material that is different than the second portion.

36. The method of claim 35 wherein the first portion is formed of a material that is different than the second portion.

37. The method of claim 35 wherein the material of the first portion has a direct effect on a threshold voltage of the first transistor.

38. The method of claim 35 wherein the material of the first portion and the material of the second portion comprise metal and polysilicon respectively.

39. The method of claim 25 wherein the first gate electrode has a T-shaped cross-section.

40. The method of claim 25 wherein the first active region is a memory cell region of the semiconductor device and wherein the second active region is a peripheral region of the semiconductor device.

41. The method of claim 25 wherein the semiconductor layer comprises a semiconductor substrate.

42. The method of claim 25 wherein the semiconductor layer is one selected from the group consisting of SOI (silicon-on-insulator), SiGe (silicon germanium), and SGOI (silicon germanium on insulator) layers.

43. The method of claim 25 wherein the vertically oriented thin body channel region is of a thickness that is selected as a function of a desired threshold voltage of the first transistor.

44. The method of claim 25 wherein the vertically oriented thin body channel region of the first transistor comprises a first lateral channel region and a second lateral channel region at opposite sides of the gate electrode in the lateral direction, each extending in a horizontal direction between the source region and the drain region.

45. The method of claim 25 wherein the second gate dielectric is of a different thickness than the first gate dielectric.

46. The method of claim 25 wherein the second gate dielectric is of a different material than the first gate dielectric.

47. The method of claim 25 wherein a threshold voltage of the first transistor and a threshold voltage of the second transistor are different.

48. The method of claim 25 further comprising providing two of the first transistors located adjacent each other in the horizontal direction in the first region, and wherein the two first transistors share a common drain region.