Insulated gate type semiconductor device and method for fabricating the same

• US 8,168,498 B2
• Filed: 12/07/2010
• Issued: 05/01/2012
• Est. Priority Date: 02/19/2001
• Status: Expired due to Term

• Current Assignee: Renesas Semiconductor Package & Test Solutions Co., Ltd. (Renesas Electronics Corporation)
• Original Assignee: Hitachi TOBU Semiconductor Limited (Hitachi, Ltd.), Renesas Electronics Corporation
• Inventors: Inagawa, Hiroshi, Machida, Nobuo, Oishi, Kentaro
• Primary Examiner(s): Chaudhari, Chandra
• Application Number:
  US12/962,499
• Publication Number:
  US 20110076818A1
• Time in Patent Office: 511 Days
• Field of Search: 438/135, 438/138, 438/589, 257/E21.384
• US Class Current: 438/270
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0615 by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] LDD or drain offset regions H01L29/7833
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/511 with a compositional variation, e.g. multilayer structures H01L29/516 takes precedence
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7821 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

In an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a semiconductor substrate, and a source-purpose conductive layer is provided on a major surface of the semiconductor substrate, a portion of a gate pillar which is constituted by both the gate-purpose conductive layer and a cap insulating film for capping an upper surface of the gate-purpose conductive layer is projected from the major surface of the semiconductor substrate; a side wall spacer is provided on a side wall of the projected portion of the gate pillar; and the source-purpose conductive layer is connected to a contact region of the major surface of the semiconductor substrate, which is defined by the side wall spacer.

Claims

1. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a major surface of a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:

a step of forming a first semiconductor region within said semiconductor substrate;

a step of forming a trench in said semiconductor substrate in such a manner that said trench penetrates said first semiconductor region;

a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within said trench;

a step in which a gate pillar made of both said gate-purpose conductive layer and a cap insulating film capping an upper surface of said gate-purpose conductive layer is formed in the trench where said gate insulating film is formed, and a portion of said gate pillar is projected from the major surface of said semiconductor substrate;

a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trench;

a step of forming a side wall spacer on both said gate-purpose conductive layer and said cap insulating film of said projected portion of said gate pillar; and

a step of forming said source-purpose conductive layer in a source contact region defined by said side wall spacer.

2. A method for manufacturing an insulated-gate type semiconductor device in which a gate-purpose conductive layer is embedded into a trench which is formed in a major surface of a semiconductor substrate, and a source-purpose conductive layer is provided on said major surface, comprising:

a step of forming a first semiconductor region within said semiconductor substrate;

a step of forming a plurality of trenches in said semiconductor substrate in such a manner that said trenches penetrate said first semiconductor region;

a step of forming a gate insulating film on a surface of said first semiconductor region which is exposed within each of said trenches;

a step in which each of said trenches where said gate insulating film is formed is embedded, and a portion of said gate-purpose conductive layer which is projected from the major surface of the semiconductor substrate is formed;

a step of forming a second semiconductor region within said first semiconductor region which is segmented by said trenches;

a step of forming a side wall spacer on a projected portion of said gate-purpose conductive layer and an insulating film covering an upper surface of said projected portion of said gate-purpose conductive layer;

a step of forming a contact hole in a source contact region defined by said side wall spacer; and

a step of forming said source-purpose conductive layer in said contact hole.

3. A method of manufacturing a semiconductor device comprising the steps of:

(a) forming a gate trench in a main surface of a semiconductor substrate of a first conductivity type;

(b) forming a gate insulating film over an inner wall and a bottom portion of the gate trench;

(c) forming a gate electrode so as to fill the gate trench and a portion of which protrudes from the semiconductor substrate such that a width of the portion of the gate electrode is not less than a width of the gate electrode in the gate trench;

(d) forming a sidewall over a side wall portion of the gate electrode protruding from the semiconductor substrate such that the height of an uppermost portion of the sidewall is higher than the height of an uppermost portion of the gate electrode;

(e) forming a second semiconductor region, in the semiconductor substrate, of a second conductivity type opposite to the first conductivity type;

(f) forming a first semiconductor region, in the semiconductor substrate, of the first conductivity type serving as a source region such that the second semiconductor region is formed below the first semiconductor region and serves as a channel region;

(g) forming a body trench between sidewalls formed on adjacent gate electrodes by self-alignment with the gate electrodes, and so as to be deeper than a depth of the first semiconductor region;

(h) forming a third semiconductor region at a bottom portion of the body trench and within the second semiconductor region, the third semiconductor region being of the second conductivity type and having an impurity concentration greater than an impurity concentration of the second semiconductor region; and

(i) forming a fourth semiconductor region in an opposite surface to the main surface of the semiconductor substrate, the fourth semiconductor region being of the first conductivity type and serving as a drain region.

4. The method according to claim 3,

wherein the sidewall is formed so as to contact the side wall portion of the gate electrode protruding from the semiconductor substrate.

5. The method according to claim 3, further comprising the step of:

forming a first insulating film over the gate electrode,

wherein the sidewall is formed over side wall portions of the first insulating film and the gate electrode protruding from the semiconductor substrate.

6. The method according to claim 3, further comprising the step of:

forming a conductive film extending over the gate electrode and electrically connected to the first semiconductor region.

7. A method of manufacturing a semiconductor device comprising the steps of:

(a) forming a gate trench in a main surface of a first portion of a semiconductor substrate, the first portion having a first conductivity type;

(b) forming a gate insulating film over an inner wall and a bottom portion of the gate trench;

(c) forming a gate electrode so as to fill the gate trench and a portion of which protrudes from the semiconductor substrate such that a width of the portion of the gate electrode is not less than a width of the gate electrode in the gate trench;

(d) forming a sidewall over a side wall portion of the gate electrode protruding from the semiconductor substrate such that the height of an uppermost portion of the sidewall is higher than the height of an uppermost portion of the gate electrode;

(e) forming a first semiconductor region, in the first portion of the semiconductor substrate, of the first conductivity type serving as a source region;

(f) forming a second semiconductor region, in the first portion of the semiconductor substrate, of a second conductivity type opposite to the first conductivity type;

(g) forming a body trench between sidewalls formed on adjacent gate electrodes by self-alignment with the gate electrodes, and so as to be deeper than a depth of the first semiconductor region;

(h) forming a third semiconductor region at a bottom portion of the body trench and within the second semiconductor region, of the second conductivity type and having an impurity concentration greater than an impurity concentration of the second semiconductor region; and

(i) forming a fourth semiconductor region in an opposite surface to the main surface of the semiconductor substrate, of the first conductivity type serving as a drain region,

the second semiconductor region being arranged below the first semiconductor region and serving as a channel region.

8. The method according to claim 7,

wherein the sidewall is formed so as to contact the side wall portion of the gate electrode protruding from the semiconductor substrate.

9. The method according to claim 7, further comprising the step of:

forming a first insulating film over the gate electrode,

wherein the sidewall is formed over side wall portions of the first insulating film and the gate electrode protruding from the semiconductor substrate.

10. The method according to claim 7, further comprising the step of:

forming a conductive film extending over the gate electrode and electrically connected to the first semiconductor region.