Pseudomorphic Si/SiGe/Si body device with embedded SiGe source/drain

• US 8,168,971 B2
• Filed: 03/25/2008
• Issued: 05/01/2012
• Est. Priority Date: 02/21/2006
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chidambarrao, Dureseti, Mocuta, Anda C., Mocuta, Dan M., Radens, Carl
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): KIM, SU C
• Application Number:
  US12/054,812
• Publication Number:
  US 20080179680A1
• Time in Patent Office: 1,498 Days
• Field of Search: 257/49, 257/66, 257/67, 257/69, 257 79- 84, 257/103, 257/195, 257/265, 257441-442, 257/E21.129, 257/E21.131, 257/E21.43, 257/E21.431, 257/E21.633, 257/E21.634, 257/E21.703, 438/199
• US Class Current: 257/49
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/1203 the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

The invention relates to a semiconductor structure and method of manufacturing and more particularly to a CMOS device with at least one embedded SiGe layer in the source/drain region of the PFET, and at least one embedded SiGe layer in the channel region of the NFET. In one embodiment, the structure of the invention enhances the electron mobility in the NFET device, and further enhances the hole mobility in the PFET device. Additionally, by using the fabrication methods and hence achieving the final structure of the invention, it is also possible to construct a PFET and NFET each with embedded SiGe layers on the same substrate.

Claims

1. A semiconductor device structure, comprising:

a substrate;

first and second gate stacks disposed on the substrate;

the first gate stack comprising at least one silicon layer, and a source/drain region adjacent to the first gate stack, the source/drain region comprising a compressive inducing material to place the first gate stack in a compressive state;

the second gate stack comprising a first silicon layer disposed on the substrate, and a tensile producing material disposed on the first silicon layer, a second silicon layer disposed on the tensile producing material to induce a tensile stress component under the second gate stack, and silicon raised source/drain regions contacting the first silicon layer, the second silicon layer and the tensile producing material, wherein the tensile producing material is a SiGe layer forming part of the second gate stack.

2. The device of claim 1, wherein the substrate comprises at least one of a silicon-on-insulator substrate and a buried oxide layer substrate.

3. The device of claim 1, wherein the second gate stack further comprises a polysilicon gate disposed on the second silicon layer.

4. The device of claim 1, wherein the compressive inducing material is SiGe material disposed laterally beside sidewalls of an SOI layer.

5. The device of claim 1, wherein:

the at least one silicon layer is formed directly on the substrate, and

the compressive inducing material is SiGe material disposed vertically above a first portion of the at least one silicon layer and laterally beside a second portion of the at least one silicon layer.

6. The device of claim 5 wherein:

the first silicon layer is disposed directly on the substrate,

the SiGe layer is disposed directly on the first silicon layer, and

the second silicon layer is disposed directly on the SiGe layer.

7. The structure as claimed in claim 1, wherein an interface between the SiGe layer and the first silicon layer is at a same level as an interface between the first silicon layer and a bottom surface of NFET source/drain regions disposed on the first silicon layer.

8. The structure as claimed in claim 1, further comprising:

a polysilicon gate formed on the at least one silicon layer, wherein the at least one silicon layer is formed directly on the substrate; and

at least one of oxide and nitride spacers arranged laterally beside the polysilicon gate and on an upper surface of and contacting the at least one silicon layer.

9. The device of claim 1, wherein the compressive inducing material is SiGe disposed in openings of an underlying SOI layer adjacent to active areas of the first gate stack.

10. A semiconductor device structure, comprising:

a NFET device and a PFET device disposed on a substrate;

the PFET device comprising a first gate stack;

the NFET device comprising a second gate stack;

wherein the first gate stack comprises at least one PFET silicon layer and an adjacent source/drain region, the source/drain region comprising at least one SiGe layer to induce a compressive stress and a source/drain silicon layer directly on the at least one SiGe layer; and

wherein the second gate stack comprises at least one NFET silicon layer formed on a SiGe layer to induce a tensile stress.

11. The structure as claimed in claim 10, wherein the substrate comprises at least one of a silicon-on-insulator substrate, and a buried oxide layer substrate.

12. The structure as claimed in claim 10, wherein the second gate stack further comprises silicon material on sides thereof to form source/drain regions.

13. The structure as claimed in claim 10, wherein:

the at least one PFET silicon layer comprises an SOI layer, and

the at least one SiGe layer to induce a compressive stress is disposed laterally beside sidewalls of the SOI layer.

14. The structure as claimed in claim 10, wherein:

the at least one PFET silicon layer is formed directly on the substrate, and

the at least one SiGe layer to induce a compressive stress comprises SiGe disposed vertically above a first portion of the at least one PFET silicon layer and laterally beside a second portion of the at least one PFET silicon layer.

15. The structure as claimed in claim 14 wherein:

the second gate stack comprises a first silicon layer disposed directly on the substrate,

the SiGe layer to induce tensile stress comprises SiGe disposed directly on the first silicon layer, and

the at least one NFET silicon layer is disposed directly on the SiGe layer to induce tensile stress.

16. The structure as claimed in claim 14, further comprising:

a gate formed on the at least one PFET silicon layer; and

at least one of oxide and nitride spacers arranged laterally beside the gate and on an upper surface of and contacting the at least one PFET silicon layer.

17. The structure as claimed in claim 10, further comprising:

a first silicon layer disposed on the substrate; and

NFET source/drain regions disposed on the first silicon layer,

wherein the SiGe layer to induce tensile stress is disposed on the first silicon layer, and

a bottom surface of the SiGe layer to induce tensile stress is at a same level as a bottom surface of the NFET source/drain regions.

18. The structure as claimed in claim 10, wherein the NFET device comprises silicon source/drain regions beside both the SiGe layer and the at least one NFET silicon layer.

19. A semiconductor device structure, comprising:

a PFET device comprising;

a PFET silicon layer including a central upper surface and lateral upper surfaces, wherein the PFET silicon layer is formed directly on a substrate and the central upper surface is higher than the lateral upper surfaces;

PFET source/drain regions comprising a first layer contacting the lateral upper surfaces of the PFET silicon layer and a first silicon layer contacting an upper surface of the first layer, wherein the first layer is composed of a material that induces compressive stress in a central portion of the PFET silicon layer;

a gate disposed on the PFET silicon layer; and

at least one of oxide and nitride spacers arranged laterally beside the gate and contacting the PFET silicon layer; and

an NFET device comprising;

an NFET silicon layer formed directly on the substrate;

a layer of tensile stress producing material disposed directly on the NFET silicon layer;

a second silicon layer disposed directly on the a layer of tensile stress producing material;

NFET source/drain regions comprising silicon contacting the NFET silicon layer, wherein a bottom surface of the layer of tensile stress producing material is at a same level as a bottom surface of the silicon of the NFET source/drain regions.

20. The semiconductor device structure of claim 19, wherein a bottom surface of the at least one of the oxide and nitride spacers is lower than an upper surface of the PFET source/drain regions.