Metal-oxide-semiconductor chip and fabrication method thereof
First Claim
1. A metal oxide semiconductor (MOS) chip, comprising:
- a heavily doped semiconductor substrate, composing a drain doped region;
an epitaxial layer, which is located on the semiconductor substrate and has an etched sidewall formed on a scribe line preserving region of the MOS chip such that the scribe line preserving region has a first portion defined on the epitaxial layer perpendicular to an upper surface of the semiconductor substrate and a second portion defined on the upper surface of the semiconductor substrate, the epitaxial layer also having an active region, and a termination region surrounding the active region and being surrounded by the scribe line preserving region, wherein the upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region is exposed;
at least a MOS cell, located in the active region and having a gate electrode and a source electrode; and
a metal pattern layer, formed on the epitaxial layer and the exposed upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region, the metal pattern layer having a gate pad, a source pad, and a drain pattern, wherein the gate pad is electrically connected to the gate electrode of the MOS cell, the source pad is electrically connected to the source electrode of the MOS cell, and the drain pattern is formed on the scribe line preserving region such that a first portion of the drain pattern is defined on the epitaxial layer perpendicular to the upper surface of the semiconductor substrate, and a second portion of the drain pattern is defined on the upper surface of the semiconductor substrate.
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Abstract
A metal-oxide-semiconductor chip having a semiconductor substrate, an epitaxial layer, at least a MOS cell, and a metal pattern layer is provided. The epitaxial layer is located on the semiconductor substrate and has an active region, a termination region, and a scribe line preserving region defined on an upper surface thereof. An etched sidewall of the epitaxial layer is located in the scribe line preserving region. The boundary portion of the upper surface of the semiconductor substrate is thus exposed. The MOS cell is located in the active region. The metal pattern layer is located on the epitaxial layer and has a gate pad coupled to the gate of the MOS cell, a source pad coupled to the source of the MOS cell, and a drain pattern, which is partly located on the upper surface of the semiconductor substrate.
18 Citations
17 Claims
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1. A metal oxide semiconductor (MOS) chip, comprising:
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a heavily doped semiconductor substrate, composing a drain doped region; an epitaxial layer, which is located on the semiconductor substrate and has an etched sidewall formed on a scribe line preserving region of the MOS chip such that the scribe line preserving region has a first portion defined on the epitaxial layer perpendicular to an upper surface of the semiconductor substrate and a second portion defined on the upper surface of the semiconductor substrate, the epitaxial layer also having an active region, and a termination region surrounding the active region and being surrounded by the scribe line preserving region, wherein the upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region is exposed; at least a MOS cell, located in the active region and having a gate electrode and a source electrode; and a metal pattern layer, formed on the epitaxial layer and the exposed upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region, the metal pattern layer having a gate pad, a source pad, and a drain pattern, wherein the gate pad is electrically connected to the gate electrode of the MOS cell, the source pad is electrically connected to the source electrode of the MOS cell, and the drain pattern is formed on the scribe line preserving region such that a first portion of the drain pattern is defined on the epitaxial layer perpendicular to the upper surface of the semiconductor substrate, and a second portion of the drain pattern is defined on the upper surface of the semiconductor substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A fabrication method of a metal-oxide-semiconductor chip, comprising the steps of:
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providing a heavily doped semiconductor substrate; forming an epitaxial layer on an upper surface of the semiconductor substrate, the epitaxial layer having a plurality of active regions, a plurality of termination regions surrounding the active regions and a scribe line preserving region defined on an upper surface thereof and surrounding the termination regions, wherein the epitaxial layer has an etched sidewall formed on the scribe line preserving region such that the scribe line preserving region has a first portion defined on the epitaxial layer perpendicular to the upper surface of the semiconductor substrate and a second portion defined on the upper surface of the semiconductor substrate, with the upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region being exposed by having a deep trench formed in the scribe line preserving region; forming a least one MOS cell in the active region, the MOS cell having a gate electrode and a source electrode; forming a metal layer on the epitaxial layer; and forming a metal pattern layer on the epitaxial layer and the exposed portion of the upper surface of the semiconductor substrate defined by the second portion of the scribe line preserving region, the metal pattern layer having at least a gate pad, a source pad, and a drain pattern, wherein the gate pad and the source pad are located in the active region and electrically connected to the gate electrode and the source electrode of the MOS cell, respectively, and the drain pattern is formed on the scribe line preserving region such that a first portion of the drain pattern is defined on the epitaxial layer perpendicular to the upper surface of the semiconductor substrate, and a second portion of the drain pattern is defined on the upper surface of the semiconductor substrate. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17)
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Specification