On-chip RF shields with through substrate conductors

• US 8,169,059 B2
• Filed: 09/30/2008
• Issued: 05/01/2012
• Est. Priority Date: 09/30/2008
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Barth, Hans-Joachim, Pohl, Jens, Beer, Gottfried, Nagy, Oliver
• Primary Examiner(s): Mandala, Victor A
• Assistant Examiner(s): Harriston, William
• Application Number:
  US12/242,521
• Publication Number:
  US 20100078771A1
• Time in Patent Office: 1,309 Days
• Field of Search: 438/637, 438/121, 438/381, 438/655, 438/667, 257/508, 257/621, 257/659, 257/531, 257/690, 257/E23.18, 257/E23.114, 257/E21.497, 257/E21.536, 257/E21.476, 174/255, 174/262, 361/818
• US Class Current: 257/659
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/552 Protection against radiation, e.g. light or electromagnetic waves
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Structures of a system on chip and methods of forming a system on chip are disclosed. In one embodiment, the system on a chip includes an RF component disposed on a first part of a substrate, a semiconductor component disposed on a second part of the substrate, the semiconductor component and the RF component sharing a common boundary. The system on chip further includes through substrate conductors disposed in the substrate, the through substrate conductors coupled to a ground potential node, the through substrate conductors disposed around the RF component forming a fence around the RF circuit.

Claims

1. A semiconductor chip comprising:

a first semiconductor component disposed on a first part of a substrate;

a second semiconductor component disposed on a second part of the substrate, the semiconductor component and the first semiconductor component sharing a common boundary;

through substrate conductors disposed in the substrate along the boundary and forming a fence around the first semiconductor component, wherein the through substrate conductors are discontinuous along an edge of the first semiconductor component in a direction parallel to a major surface of the substrate, and wherein the through substrate conductors are arranged in a staggered formation in multiple rows around the first semiconductor component, wherein each one of the through substrate conductors comprises a shallow cylinder near the top surface of the substrate and a deep cylinder extending through the substrate, the top surface comprising active devices, wherein the shallow and deep cylinders are concentric; and

a ground potential node coupled to the through substrate conductors.

2. The semiconductor chip of claim 1, wherein the first semiconductor component comprises a radio frequency component.

3. The semiconductor chip of claim 1, wherein the through substrate conductors are lined with a dielectric liner and filled with a conductive material.

4. The semiconductor chip of claim 3, wherein the conductive material comprises a metal selected from a group consisting of copper, gold, silver, aluminum, tungsten, polysilicon and combinations thereof.

5. The semiconductor chip of claim 1, wherein a longer side of the through substrate conductors is aligned along the edge of the first semiconductor component.

6. The semiconductor chip of claim 1, wherein the through substrate conductors are staggered between the multiple rows.

7. The semiconductor chip of claim 1, wherein the through substrate conductors are spaced apart by a distance of less than about 300 μ

m.

8. The semiconductor chip of claim 1, wherein the through substrate conductors comprise vias or trenches.

12. The semiconductor chip of claim 1, wherein the through substrate conductors are designed to shield the second semiconductor component from electromagnetic radiation emitted by the first semiconductor component.

14. The semiconductor chip of claim 1, further comprising back side contacts coupled to the through substrate conductors, the back side contacts disposed on the back side of the substrate.

15. The semiconductor chip of claim 14, wherein the back side contacts are electrically coupled to another semiconductor chip.

16. The semiconductor chip of claim 15, wherein the another semiconductor chip comprises another through substrate conductor, the another through substrate conductor coupled to the through substrate conductors through the back side contacts.

9. A semiconductor chip comprising:

a first semiconductor component disposed on a first part of a substrate;

a second semiconductor component disposed on a second part of the substrate, the semiconductor component and the first semiconductor component sharing a common boundary;

through substrate conductors disposed in the substrate along the boundary and foaming a fence around the first semiconductor component, wherein the through substrate conductors are discontinuous along an edge of the first semiconductor component in a direction parallel to a major surface of the substrate, and wherein the through substrate conductors are arranged in a staggered formation in multiple rows around the first semiconductor component, wherein a width of the through substrate conductors is larger near a top surface of the substrate than a width of the through substrate conductors on a bottom surface, the top surface comprising active devices and being opposite the bottom surface;

a ground potential node coupled to the through substrate conductors; and

another through substrate conductor, wherein a width of the another through substrate conductor is smaller near the top surface of the substrate than a width of the another through substrate conductor on the bottom surface.

10. The semiconductor chip of claim 9, wherein each one of the through substrate conductors comprises a trench disposed adjacent the top surface of the substrate and a deep cylinder disposed within the trench, the deep cylinder extending from the top surface to an opposite bottom surface.

11. The semiconductor chip of claim 10, wherein the trench of each of the through substrate conductors is electrically connected to at least one adjacent trench of the through substrate conductors.

29. The semiconductor chip of claim 9, wherein the first semiconductor component comprises a radio frequency component.

30. The semiconductor chip of claim 9, wherein the through substrate conductors are lined with a dielectric liner and filled with a conductive material.

31. The semiconductor chip of claim 30, wherein the conductive material comprises a metal selected from a group consisting of copper, gold, silver, aluminum, tungsten, polysilicon and combinations thereof.

32. The semiconductor chip of claim 9, wherein the through substrate conductors are spaced apart by a distance of less than about 300 μ

m.

33. The semiconductor chip of claim 9, wherein the through substrate conductors are designed to shield the second semiconductor component from electromagnetic radiation emitted by the first semiconductor component.

13. A semiconductor chip comprising:

a first semiconductor component disposed on a first part of a substrate;

a second semiconductor component disposed on a second part of the substrate, the semiconductor component and the first semiconductor component sharing a common boundary;

through substrate conductors disposed in the substrate along the boundary and forming a fence around the first semiconductor component, wherein the through substrate conductors are discontinuous along an edge of the first semiconductor component in a direction parallel to a major surface of the substrate, and wherein the through substrate conductors are arranged in a staggered formation in multiple rows around the first semiconductor component;

additional trenches disposed in the substrate electrically coupling the first semiconductor component with the second semiconductor component through openings between the through substrate conductors, wherein the additional trenches make no connection to the through substrate conductors; and

a ground potential node coupled to the through substrate conductors.

34. The semiconductor chip of claim 13, wherein the first semiconductor component comprises a radio frequency component.

35. The semiconductor chip of claim 13, wherein the through substrate conductors are lined with a dielectric liner and filled with a conductive material.

36. The semiconductor chip of claim 35, wherein the conductive material comprises a metal selected from a group consisting of copper, gold, silver, aluminum, tungsten, polysilicon and combinations thereof.

37. The semiconductor chip of claim 13, wherein the through substrate conductors are spaced apart by a distance of less than about 300 μ

m.

38. The semiconductor chip of claim 13, wherein the through substrate conductors comprise vias or trenches.

39. The semiconductor chip of claim 13, wherein the through substrate conductors are designed to shield the second semiconductor component from electromagnetic radiation emitted by the first semiconductor component.

40. The semiconductor chip of claim 13, further comprising back side contacts coupled to the through substrate conductors, the back side contacts disposed on the back side of the substrate.

41. The semiconductor chip of claim 40, wherein the back side contacts are electrically coupled to another semiconductor chip.

42. The semiconductor chip of claim 41, wherein the another semiconductor chip comprises another through substrate conductor, the another through substrate conductor coupled to the through substrate conductors through the back side contacts.

17. A semiconductor chip comprising:

first through substrate conductors disposed around a first circuit disposed on the semiconductor chip, the first through substrate conductors coupled to a ground potential node; and

second through substrate conductors disposed around a second circuit disposed on the semiconductor chip, the second through substrate conductors are electrically floating.

18. The semiconductor chip of claim 17, wherein the first circuit comprises a radio frequency circuit, and the second circuit comprises a high performance circuit.

19. The semiconductor chip of claim 17, wherein the first through substrate conductors are designed to shield the first circuit to and/or from RF radiation and wherein the second through substrate conductors are designed to remove heat generated by the second circuit.

20. The semiconductor chip of claim 17, wherein the first and second through substrate conductors comprise at least one different dimension.

21. A semiconductor chip comprising:

a first circuit disposed in a first region of a substrate, the first circuit being disposed on a top surface of the substrate; and

through substrate conductors disposed in a second region of the substrate, the through substrate conductors disposed around the first circuit, the second region comprising no active devices, wherein the through substrate conductors are designed to remove heat generated by the first circuit.

22. The semiconductor chip of claim 21, wherein the first circuit comprises a high performance circuit.

23. The semiconductor chip of claim 21, wherein the through substrate conductors are electrically floating.

24. The semiconductor chip of claim 21, wherein the through substrate conductors each have a diameter that is wider adjacent the top surface than adjacent a bottom surface of the substrate, the bottom surface being opposite the top surface.

25. A method of forming a semiconductor chip, the method comprising:

forming a through substrate opening from a front surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry;

forming the active regions before forming the through substrate opening, the active regions comprising the first region and the second region;

filling the through substrate opening with a conductive material;

forming interconnect layers after forming the through substrate opening, the interconnect layers interconnecting the active regions;

exposing the conductive material in the through substrate opening by thinning the substrate, the back surface being opposite to the front surface; and

electrically coupling the conductive material with a ground potential node.

26. A method of forming a semiconductor chip, the method comprising:

forming a through substrate opening from a front surface of a substrate, the through substrate opening disposed between a first and a second region, the first region comprising devices for RF circuitry and the second region comprising devices for other circuitry;

filling the through substrate opening with a conductive material;

exposing the conductive material in the through substrate opening by thinning the substrate, the back surface being opposite to the front surface;

electrically coupling the conductive material with a ground potential node;

depositing an insulating layer on the back surface;

depositing and patterning a first photo resist layer on the insulating layer, the patterned first photo resist layer exposing a back contact of the through substrate opening;

depositing a conductive liner over the first photo resist layer, the barrier liner contacting the back contact;

depositing and patterning a second photo resist layer on the conductive liner, the patterned second photo resist layer forming patterns for redistribution lines; and

forming redistribution lines by filling the patterned second photo resist layer with the conductive material.

27. The method of claim 26, further comprising:

etching portions of the conductive liner not covered by the conductive material; and

depositing a passivation dielectric layer between the redistribution lines.

28. The method of claim 26, wherein filling the patterned second photo resist layer with the conductive material comprises filling by electroplating the conductive material.