Semiconductor devices including first and second silicon interconnection regions
First Claim
Patent Images
1. A semiconductor device comprising:
- a first interconnection including a first silicon interconnection region and a first metal interconnection region stacked sequentially on a substrate; and
a second interconnection including a second silicon interconnection region and a second metal interconnection region stacked sequentially on the substrate,wherein a bottom surface of the second silicon interconnection region is disposed at substantially the same level as a bottom surface of the first silicon interconnection region, andwherein the second silicon interconnection region has a lower resistivity than the first silicon interconnection region.
1 Assignment
0 Petitions
Accused Products
Abstract
Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first interconnection disposed on a substrate. The interconnection includes a first silicon interconnection region and a first metal interconnection region sequentially stacked on the substrate. A second interconnection includes a second silicon interconnection region and a second metal interconnection region that are stacked sequentially. The second silicon interconnection region has a lower resistivity than the first silicon interconnection region.
-
Citations
20 Claims
-
1. A semiconductor device comprising:
-
a first interconnection including a first silicon interconnection region and a first metal interconnection region stacked sequentially on a substrate; and a second interconnection including a second silicon interconnection region and a second metal interconnection region stacked sequentially on the substrate, wherein a bottom surface of the second silicon interconnection region is disposed at substantially the same level as a bottom surface of the first silicon interconnection region, and wherein the second silicon interconnection region has a lower resistivity than the first silicon interconnection region. - View Dependent Claims (2, 3, 4, 5, 6)
-
-
7. A semiconductor device comprising:
-
a semiconductor substrate having first and second circuit regions; a first MOS transistor disposed on the first circuit region of the semiconductor substrate and including a first gate structure and first source and drain regions; a contact region electrically connected to one of the first source and drain regions; a first silicon interconnection region connected to the contact region and having a higher resistivity than the contact region; a first metal interconnection region disposed on the contact region and the first silicon interconnection region; a second silicon interconnection region disposed on the second circuit region of the semiconductor substrate and having a lower resistivity than the first silicon interconnection region; and a second metal interconnection region disposed on the second silicon interconnection region. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
-
-
20. A semiconductor device comprising:
-
a semiconductor substrate having first and second circuit regions; a first MOS transistor disposed on the first circuit region of the semiconductor substrate and including a first gate structure and first source and drain regions; a contact region electrically connected to one of the first source and drain regions; a first silicon interconnection region connected to the contact region and having a higher resistivity than the contact region; a first metal interconnection region disposed on the first silicon interconnection region; a second silicon interconnection region disposed on the second circuit region of the semiconductor substrate and having a lower resistivity than the first silicon interconnection region; and a second metal interconnection region disposed on the second silicon interconnection region, wherein the first silicon interconnection includes a first portion and a second portion spaced apart from each other, wherein the contact region is interposed between the first portion of the first silicon interconnection and the second portion of the first silicon interconnection, wherein a bottom surface of the second silicon interconnection region is disposed at substantially the same level as a bottom surface of the first silicon interconnection region, and wherein the first silicon interconnection region is disposed at a higher level than the first gate structure.
-
Specification