Semiconductor devices including first and second silicon interconnection regions

• US 8,169,074 B2
• Filed: 06/30/2010
• Issued: 05/01/2012
• Est. Priority Date: 07/23/2009
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Park, Jong-Man, Yamada, Santoru
• Primary Examiner(s): Le, Thao
• Assistant Examiner(s): ZHU, SHENG-BAI
• Application Number:
  US12/827,375
• Publication Number:
  US 20110020993A1
• Time in Patent Office: 671 Days
• Field of Search: 257/E21.616, 257/E21.637, 257/E27.062, 257/369, 438/275, 438/243, 438/155
• US Class Current: 257/734
• CPC Class Codes: H01L 21/823437 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects

Abstract

Provided are a semiconductor device and a method of fabricating the same. The semiconductor device includes a first interconnection disposed on a substrate. The interconnection includes a first silicon interconnection region and a first metal interconnection region sequentially stacked on the substrate. A second interconnection includes a second silicon interconnection region and a second metal interconnection region that are stacked sequentially. The second silicon interconnection region has a lower resistivity than the first silicon interconnection region.

Claims

1. A semiconductor device comprising:

a first interconnection including a first silicon interconnection region and a first metal interconnection region stacked sequentially on a substrate; and

a second interconnection including a second silicon interconnection region and a second metal interconnection region stacked sequentially on the substrate,

wherein a bottom surface of the second silicon interconnection region is disposed at substantially the same level as a bottom surface of the first silicon interconnection region, and

wherein the second silicon interconnection region has a lower resistivity than the first silicon interconnection region.

2. The device of claim 1, wherein the first silicon interconnection region is formed of undoped silicon or intrinsic silicon, and the second silicon interconnection region is formed of doped silicon.

3. The device of claim 1, wherein the first and second silicon interconnection regions are formed of doped silicon of the same conductivity type, and the second silicon interconnection region is formed of doped silicon having a higher dopant concentration than the first silicon interconnection region.

4. The device of claim 1, further comprising a doped silicon buffer region interposed between the first silicon interconnection region and the first metal interconnection region and having a lower resistivity than the first silicon interconnection region.

5. The device of claim 1, wherein the first silicon interconnection region has a smaller width than the second silicon interconnection region.

6. The device of claim 1, further comprising:

a first metal buffer region interposed between the first silicon interconnection region and the first metal interconnection region; and

a second metal buffer region interposed between the second silicon interconnection region and the second metal interconnection region,

wherein a thickness of the first silicon interconnection region is greater than a thickness of the first metal buffer region, and

wherein a thickness of the second silicon interconnection region is greater than a thickness of the second metal buffer region.

7. A semiconductor device comprising:

a semiconductor substrate having first and second circuit regions;

a first MOS transistor disposed on the first circuit region of the semiconductor substrate and including a first gate structure and first source and drain regions;

a contact region electrically connected to one of the first source and drain regions;

a first silicon interconnection region connected to the contact region and having a higher resistivity than the contact region;

a first metal interconnection region disposed on the contact region and the first silicon interconnection region;

a second silicon interconnection region disposed on the second circuit region of the semiconductor substrate and having a lower resistivity than the first silicon interconnection region; and

a second metal interconnection region disposed on the second silicon interconnection region.

8. The device of claim 7, wherein the first MOS transistor comprises:

first source and drain regions disposed in a first active region defined by an isolation region formed in the semiconductor substrate, the first source and drain regions spaced apart from each other; and

a first gate structure configured to partially fill a gate trench that runs across the first active region between the first source and drain regions and extends to the isolation region,

wherein the first and second silicon interconnection regions are disposed at a higher level than the first gate structure.

9. The device of claim 8, wherein the first gate structure partially fills the gate trench disposed across the first active region and extends to the isolation region to cover sidewalls of the first active region at a lower level than a bottom region of the gate trench of the first active region.

10. The device of claim 8, further comprising a second MOS transistor disposed on the second circuit region of the semiconductor substrate and including a second gate structure and second source and drain regions,

wherein the second MOS transistor includes:

a second gate dielectric layer and a second gate structure stacked sequentially on a second active region defined by the isolation region disposed in the semiconductor substrate; and

second source and drain regions disposed in the second active region on both sides of the second gate structure,

wherein the second gate structure includes the second silicon interconnection region and the second metal interconnection region.

11. The device of claim 7, wherein a bottom surface of the second silicon interconnection region is disposed at substantially the same level with a bottom surface of the first silicon interconnection region, and the second metal interconnection region is formed of the same material as the first metal interconnection region.

12. The device of claim 7, wherein the first and second silicon interconnection regions are formed of doped silicon of the same conductivity type, and the second silicon interconnection region is formed of doped silicon having a higher dopant concentration than the first silicon interconnection region.

13. The device of claim 7, wherein the contact region is formed of doped silicon or the same material as the first metal interconnection region.

14. The device of claim 7, wherein the first silicon interconnection region is formed of undoped silicon or intrinsic silicon.

15. The device of claim 7, further comprising a doped silicon buffer region interposed between the first silicon interconnection region and the first metal interconnection region and having a lower resistivity than the first silicon interconnection region.

16. The device of claim 7, wherein a width of the contact region is greater than a width of the first silicon interconnection region.

17. The device of claim 7, wherein the first silicon interconnection region includes a first portion and a second portion,

wherein the first portion of the first silicon interconnection region is spaced apart from the second portion of the first silicon interconnection region,

wherein the contact region is interposed between the first portion of the first silicon interconnection region and the second portion of the first silicon interconnection region.

18. The device of claim 7, wherein a top surface of the contact region is disposed at a higher level than a top surface of the first silicon interconnection region.

19. The device of claim 7, wherein a bottom surface of the contact region is disposed at a lower level than a bottom surface of the first silicon interconnection region.

20. A semiconductor device comprising:

a semiconductor substrate having first and second circuit regions;

a first MOS transistor disposed on the first circuit region of the semiconductor substrate and including a first gate structure and first source and drain regions;

a contact region electrically connected to one of the first source and drain regions;

a first silicon interconnection region connected to the contact region and having a higher resistivity than the contact region;

a first metal interconnection region disposed on the first silicon interconnection region;

a second silicon interconnection region disposed on the second circuit region of the semiconductor substrate and having a lower resistivity than the first silicon interconnection region; and

a second metal interconnection region disposed on the second silicon interconnection region,

wherein the first silicon interconnection includes a first portion and a second portion spaced apart from each other,

wherein the contact region is interposed between the first portion of the first silicon interconnection and the second portion of the first silicon interconnection,

wherein a bottom surface of the second silicon interconnection region is disposed at substantially the same level as a bottom surface of the first silicon interconnection region, and

wherein the first silicon interconnection region is disposed at a higher level than the first gate structure.