Conductive routings in integrated circuits using under bump metallization

• US 8,169,081 B1
• Filed: 12/23/2008
• Issued: 05/01/2012
• Est. Priority Date: 12/27/2007
• Status: Active Grant

• Current Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Original Assignee: Volterra Semiconductor Corporation (Analog Devices, Inc.)
• Inventors: Jergovic, Ilija, Lacap, Efren M.
• Primary Examiner(s): VU, HUNG K
• Application Number:
  US12/343,261
• Time in Patent Office: 1,225 Days
• Field of Search: 257/341, 257/434, 257/401, 257/786, 257/343, 257/758, 257/773, 257/E23.06, 257/E23.011, 257/E29.12, 257/E29.268, 257/E29.279
• US Class Current: 257/773
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05624 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 23/4824 Pads with extended contours, e.g. grid structure, branch structure, finger structure
• CPC Class Codes: H01L 23/522 including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01014 Silicon [Si]
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

An integrated circuit structure includes a first conductive layer and an under bump metallization layer over the first conductive layer. The first conductive layer has a first conductive region and a second conductive region electrically isolated from the first conductive region. The under bump metallization layer has a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region. At least one of the first conductive area or the first conductive region includes a first protrusion extending toward the second conductive area or second conductive region, respectively. Conductive vias connect the first conductive region to the second conductive area and connect the second conductive region to the first conductive area, and the vias include at least one via connected to the first protrusion.

Claims

1. An integrated circuit structure comprising:

a first conductive layer below an uppermost passivation layer, the first conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region;

an under bump metallization layer over the first conductive layer, the under bump metallization layer extending over the uppermost passivation layer, the under bump metallization layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region;

at least one of the first conductive area or the first conductive region including a first protrusion extending toward the second conductive area or second conductive region, respectively; and

conductive vias through the uppermost passivation layer connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, the conductive vias including at least one via connected to the first protrusion.

2. The integrated circuit structure of claim 1, wherein the first conductive area includes the first protrusion extending toward the second conductive area.

3. The integrated circuit structure of claim 2, wherein the first conductive region includes a second protrusion extending toward the second conductive region, and the conductive vias include at least one via connected to the second protrusion.

4. The integrated circuit structure of claim 1, wherein the first conductive region includes the first protrusion extending toward the second conductive region.

5. The integrated circuit structure of claim 1, further comprising a first flip-chip interconnect on the first conductive area of the under bump metallization layer and a second flip-chip interconnect on the second conductive area of the under bump metallization layer.

6. The integrated circuit structure of claim 5, wherein the first flip-chip interconnect and second flip-chip interconnect are solder bumps, solder balls, copper pillars or stud bumps.

7. The integrated circuit structure of claim 1, wherein the first conductive region has a plurality of first protrusions extending toward the second conductive region, and the second conductive region has a plurality of second protrusions extending toward the first conductive region.

8. The integrated circuit structure of claim 7, wherein the first conductive area has a plurality of third protrusions extending toward the second conductive area, and the second conductive area has a plurality of fourth protrusions extending toward the first conductive area.

9. The integrated circuit structure of claim 8, wherein a plurality of first conductive vias connect the plurality of first protrusions to the plurality of fourth protrusions and a plurality of second conductive vias connect the plurality of second protrusions to the plurality of third protrusions.

10. The integrated circuit structure of claim 1, wherein the first conductive area has a plurality of first protrusions extending toward the second conductive area, and the second conductive area has a plurality of second protrusions extending toward the first conductive area.

11. The integrated circuit structure of claim 1, wherein the under bump metallization includes a contact layer to contact a portion of the first conductive layer and an outer layer.

12. The integrated circuit structure of claim 11, further comprising an intermediate layer between the contact layer and the outer layer.

13. The integrated circuit structure of claim 12, wherein the intermediate layer comprises a diffusion-blocking material.

14. The integrated circuit structure of claim 13, wherein the contact layer comprises aluminum, the intermediate layer comprises a nickel vanadium alloy, and the outer layer comprises copper.

15. The integrated circuit structure of claim 11, wherein the contact layer comprises titanium and the outer layer comprises copper.

16. The integrated circuit structure of claim 11, wherein the outer layer comprises a metal layer having a thickness greater than 6 microns.

17. The integrated circuit structure of claim 16, wherein the outer layer comprises copper.

18. The integrated circuit structure of claim 1, wherein the integrated circuit structure further comprises a substrate under the first conductive layer, the substrate having a first distributed transistor with a first plurality of doped source regions and a first plurality of doped drain regions, and the first conductive region and the second conductive area are electrically coupled to the first plurality of doped source regions and the second conductive region and the first conductive area are electrically coupled to the first plurality of doped drain regions.

19. The integrated circuit structure of claim 18, wherein the first plurality of doped source regions and the first plurality of doped drain regions are arranged in an alternating pattern in the substrate.

20. The integrated circuit structure of claim 19, further comprising

a second distributed transistor with a second plurality of doped source regions and a second plurality of doped drain regions arranged in an alternating pattern in the substrate,

and wherein

the first conductive layer has a third conductive region and a fourth conductive region electrically isolated from the third conductive region,

the under bump metallization layer has a third conductive area and a fourth conductive area electrically isolated from the third conductive area, the third conductive area substantially located over the third conductive region and the second conductive area substantially located over the fourth conductive region,

at least one of the third conductive area or the third conductive region including a second protrusion extending toward the fourth conductive area or fourth conductive region, respectively,

the conductive vias connect the third conductive region to the fourth conductive area and connect the fourth conductive region to the third conductive area, the conductive vias including at least one via connected to the second protrusion, and

the third conductive region and the fourth conductive electrically coupled to the second plurality of doped source regions and the fourth conductive region and the third conductive area electrically coupled to the second plurality of doped drain regions.

21. The integrated circuit structure of claim 20, wherein the first conductive area is electrically coupled to the third conductive area.

22. The integrated circuit structure of claim 20, wherein the first conductive area is electrically coupled to the fourth conductive area.

23. The integrated circuit structure of claim 20, wherein the second conductive area is electrically coupled to the fourth conductive area.

24. The integrated circuit structure of claim 20, further comprising a first flip-chip interconnect on the first conductive area of the under bump metallization layer, a second flip-chip interconnect on the second conductive area of the under bump metallization layer, a third flip-chip interconnect on the third conductive area of the under bump metallization layer, and a fourth flip-chip interconnect on the fourth conductive area of the under bump metallization layer.

25. The integrated circuit structure of claim 18, further comprising a second conductive layer between the first conductive layer and the substrate, the second conductive layer including a plurality of first conductive portions and a plurality of second conductive portions disposed below the first conductive region, and including a plurality of third conductive portions and a plurality of fourth conductive portions disposed below the first conductive region.

26. The integrated circuit structure of claim 25, further comprising a third plurality of vias connecting the first conductive region to the plurality of first conductive portions and a fourth plurality of vias connecting the second conductive region to the plurality of third conductive portions.

27. The integrated circuit structure of claim 26, further comprising a fifth plurality of vias connecting the first conductive area to the plurality of second conductive portions and a sixth plurality of vias connecting the second conductive area to the plurality of fourth conductive portions.

28. An integrated circuit structure comprising:

a first conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region;

a second conductive layer over the first conductive layer, the second conductive layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region;

only one of the first conductive area or the first conductive region including a first protrusion extending toward the second conductive area or second conductive region, respectively; and

conductive vias connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, the conductive vias including at least one via connected to the first protrusion.

29. The integrated circuit structure of claim 28, wherein the first conductive area includes the first protrusion extending toward the second conductive area.

30. The integrated circuit structure of claim 28, wherein the first conductive region includes the first protrusion extending toward the second conductive region.

31. The integrated circuit structure of claim 28, wherein the first conductive region has a plurality of first protrusions extending toward the second conductive region, and the second conductive region has a plurality of second protrusions extending toward the first conductive region.

32. The integrated circuit structure of claim 31, wherein the first conductive area has a plurality of third protrusions extending toward the second conductive area, and the second conductive area has a plurality of fourth protrusions extending toward the first conductive area.

33. The integrated circuit structure of claim 32, wherein a plurality of first conductive vias connect the plurality of first protrusions to the plurality of fourth protrusions and a plurality of second conductive vias connect the plurality of second protrusions to the plurality of third protrusions.

34. The integrated circuit structure of claim 28, wherein the first conductive area has a plurality of first protrusions extending toward the second conductive area, and the second conductive area has a plurality of second protrusions extending toward the first conductive area.

35. The integrated circuit structure of claim 28, wherein the integrated circuit structure further comprises a substrate under the first conductive layer, the substrate having a first plurality of doped source regions and a second plurality of doped drain regions, and the first conductive region and the second conductive area are electrically coupled to the first plurality of doped source regions and the second conductive region and the first conductive area are electrically coupled to the first plurality of doped drain regions.

36. An integrated circuit structure comprising:

a first conductive layer below an uppermost passivation layer, the first conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region;

a second conductive layer under the first conductive layer, the second conductive layer including a first conductive portion and a second conductive portion electrically isolated from the first conductive portion, the first conductive portion disposed below the first conductive region, the second conductive portion disposed below the second conductive region;

an under bump metallization layer over the first conductive layer, the under bump metallization layer extending over the uppermost passivation layer, the under bump metallization layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area substantially located over the first conductive region and the second conductive area substantially located over the second conductive region;

a first conductive via connecting the first conductive area to the first conductive portion, the first conductive via passing through the uppermost passivation layer and passing through an aperture in and electrically isolated from the first conductive region; and

conductive vias including first vias through the uppermost passivation layer connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, and second vias connecting the first conductive portion to the second conductive region and connecting the second conductive portion to the first conductive region.

37. The integrated circuit structure of claim 36, further comprising a second conductive via connecting the second conductive area to the second conductive portion, the second conductive via passing through an aperture in and electrically isolated from the second conductive region.

38. An integrated circuit structure comprising:

a first conductive layer below an uppermost passivation layer, the first conductive layer having a first conductive region and a second conductive region electrically isolated from the first conductive region;

a second conductive layer under the first conductive layer, the second conductive layer including a first conductive portion and a second conductive portion electrically isolated from the first conductive portion, the first conductive portion disposed below and substantially overlapping the first conductive region, the second conductive portion disposed below and substantially overlapping the second conductive region;

an under bump metallization layer over the first conductive layer, the under bump metallization layer extending over the uppermost passivation layer, the under bump metallization layer having a first conductive area and a second conductive area electrically isolated from the first conductive area, the first conductive area disposed over and substantially overlapping the first conductive region and the second conductive area disposed over the second conductive region;

at least one of the first conductive area, first conductive region or first conductive portion including a protrusion extending toward the second conductive region, second conductive area or second conductive portion, respectively; and

conductive vias including first vias through the uppermost passivation layer connecting the first conductive region to the second conductive area and connecting the second conductive region to the first conductive area, and second vias connecting the first conductive portion to the second conductive region and connecting the second conductive portion to the first conductive region, the conductive vias including at least one via connected to the protrusion.