Semiconductor device and method for manufacturing the same

• US 8,169,082 B2
• Filed: 11/02/2011
• Issued: 05/01/2012
• Est. Priority Date: 12/17/2008
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: DENSO Corporation
• Inventors: Fujii, Tetsuo, Yamanaka, Akitoshi, Yokura, Hisanori
• Primary Examiner(s): Ho, Tu-Tu
• Application Number:
  US13/287,188
• Publication Number:
  US 20120049381A1
• Time in Patent Office: 181 Days
• Field of Search: 257/777, 257/688, 257/692, 257/739, 257/776, 257/415, 257/E23.016, 438/117, 438/118, 438/51
• US Class Current: 257/777
• CPC Class Codes: B81B 2207/097 Interconnects arranged on the substrate or the lid, and covered by the package seal
• CPC Class Codes: B81B 7/007 Interconnections between the MEMS and external electrical signals
• CPC Class Codes: G01C 19/5719 using planar vibrating masses driven in a translation vibration along an axis
• CPC Class Codes: G01C 19/5783 Mountings or housings not specific to any of the devices covered by groups G01C19/5607 - G01C19/5719
• CPC Class Codes: G01P 15/0802 Details
• CPC Class Codes: G01P 15/125 by capacitive pick-up
• CPC Class Codes: G01P 2015/0814 for translational movement of the mass, e.g. shuttle type
• CPC Class Codes: H01L 2224/023 Redistribution layers [RDL] for bonding areas
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05558 conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/114 by blanket deposition of the material of the bump connector
• CPC Class Codes: H01L 2224/116 by patterning a pre-deposited material
• CPC Class Codes: H01L 2224/13009 Bump connector integrally formed with a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13011 comprising apertures or cavities, e.g. hollow bump
• CPC Class Codes: H01L 2224/13025 the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/2518 being disposed on at least two different sides of the body, e.g. dual array
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48 : of an individual wire connector
• CPC Class Codes: H01L 2224/48463 : the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/80001 : by connecting a bonding area directly to another bonding area, i.e. connectorless bonding, e.g. bumpless bonding
• CPC Class Codes: H01L 2224/81805 : involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/12 : Structure, shape, material or disposition of the bump connectors prior to the connecting process
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 24/45 : of an individual wire connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/94 : at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/16 : the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0001 : Technical content checked by a classifier
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01018 : Argon [Ar]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01032 : Germanium [Ge]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01072 : Hafnium [Hf]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10157 : at the active surface
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/10329 : Gallium arsenide [GaAs]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/1461 : MEMS
• CPC Class Codes: H01L 2924/15747 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2924/15787 : Ceramics, e.g. crystalline carbides, nitrides or oxides
• CPC Class Codes: H01L 2924/15788 : Glasses, e.g. amorphous oxides, nitrides or fluorides
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30105 : Capacitance
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding

Abstract

A semiconductor device includes: a sensor including a sensor structure on a first side of the sensor and a periphery element surrounding the sensor structure; and a cap covering the sensor structure and having a second side bonded to the first side of the sensor. The cap includes a first wiring layer on the second side of the cap. The first wiring layer steps over the periphery element. The sensor further includes a sensor side connection portion, and the cap further includes a cap side connection portion. The sensor side connection portion is bonded to the cap side connection portion. At least one of the sensor side connection portion and the cap side connection portion provides an eutectic alloy so that the sensor side connection portion and the cap side connection portion are bonded to each other.

Claims

1. A semiconductor device comprising:

a first chip having a plate shape with a first side and including a first IC circuit, which is disposed on the first side of the first chip; and

a second chip having a plate shape with a second side and including a second IC circuit, which is disposed on the second side of the second chip,

wherein the first chip further includes;

a first insulation film disposed on the first IC circuit;

a first wiring layer disposed on the first insulation film and coupled with the first IC circuit;

a second insulation film disposed on the first wiring layer and having a first opening for exposing the first wiring layer from the second insulation film; and

a second wiring layer disposed on the first wiring layer exposed from the second insulation film via the first opening,

wherein the second wiring layer includes a first concavity, which is disposed over the first opening and is concaved toward the first opening,

wherein the second chip further includes;

a third insulation film disposed on the second IC circuit;

a third wiring layer disposed on the third insulation film and coupled with the second IC circuit;

a fourth insulation film disposed on the third wiring layer and having a second opening for exposing the third wiring layer from the fourth insulation film; and

a fourth wiring layer disposed on the third wiring layer exposed from the fourth insulation film via the second opening,

wherein the fourth wiring layer includes a second concavity, which is disposed over the second opening and is concaved toward the second opening,

wherein the first concavity of the second wiring layer faces the second concavity of the fourth wiring layer, and

wherein the second wiring layer of the first chip is bonded to the fourth wiring layer of the second chip so that the first side of the first chip is coupled with the second side of the second chip.

2. The semiconductor device according to claim 1,

wherein the second wiring layer of the first chip further includes a first sealing portion having a ring shape,

wherein the first sealing portion is disposed on the second insulation film, and is electrically isolated from the first wiring layer,

wherein the fourth wiring layer of the second chip further includes a second sealing portion having a ring shape,

wherein the second sealing portion is disposed on the fourth insulation film, and is electrically isolated from the third wiring layer, and

wherein the first sealing portion of the first chip is bonded to the second sealing portion of the second chip so that the first and second sealing portions and the first to fourth insulation films provide a sealed space.

3. A method for manufacturing a semiconductor device comprising:

forming a first IC circuit on a first side of a first chip having a plate shape;

forming a first insulation film on the first IC circuit;

forming a first wiring layer on the first insulation film and coupling the first wiring layer and the first IC circuit;

forming a second insulation film on the first wiring layer;

forming a first opening in the second insulation film in such a manner that the first wiring layer is exposed from the second insulation film via the first opening;

forming a second wiring layer on the first wiring layer exposed from the second insulation film via the first opening, wherein the second wiring layer includes a first concavity, which is disposed over the first opening and is concaved toward the first opening;

forming a second IC circuit on a second side of a second chip having a plate shape;

forming a third insulation film on the second IC circuit;

forming a third wiring layer on the third insulation film and coupling the third wiring layer and the second IC circuit;

forming a fourth insulation film on the third wiring layer;

forming a second opening in the fourth insulation film in such a manner that the third wiring layer is exposed from the fourth insulation film via the second opening;

forming a fourth wiring layer on the third wiring layer exposed from the fourth insulation film via the second opening, wherein the fourth wiring layer includes a second concavity, which is disposed over the second opening and is concaved toward the second opening;

facing the first concavity of the second wiring layer and the second concavity of the fourth wiring layer; and

bonding the second wiring layer of the first chip and the fourth wiring layer of the second chip so that the first side of the first chip is coupled with the second side of the second chip.

4. The method according to claim 3,

wherein the forming the second wiring layer of the first chip includes forming a first sealing portion having a ring shape on the second insulation film,

wherein the first sealing portion is electrically isolated from the first wiring layer,

wherein the forming the fourth wiring layer of the second chip includes forming a second sealing portion having a ring shape on the fourth insulation film,

wherein the second sealing portion is electrically isolated from the third wiring layer, and

wherein the bonding the second wiring layer of the first chip and the fourth wiring layer of the second chip includes:

bonding the first sealing portion of the first chip and the second sealing portion of the second chip; and

sealing a space between the first and second sealing portions and the first to fourth insulation films.