Programming of DIMM termination resistance values

• US 8,169,233 B2
• Filed: 06/09/2010
• Issued: 05/01/2012
• Est. Priority Date: 06/09/2009
• Status: Active Grant

• Current Assignee: Google LLC (Alphabet Inc.)
• Original Assignee: Google Inc. (Alphabet Inc.)
• Inventors: Ferolito, Philip Arnold, Rosenband, Daniel L., Wang, David T., Smith, Michael John Sebastian
• Primary Examiner(s): Ismail, Shawki
• Assistant Examiner(s): WHITE, DYLAN C
• Application Number:
  US12/797,557
• Publication Number:
  US 20110095783A1
• Time in Patent Office: 692 Days
• Field of Search: 326/30, 365/63, 365/51, 365/198, 365/191
• US Class Current: 326/30
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.

Claims

1. An apparatus for providing termination resistance in a memory module, the apparatus comprising:

a plurality of memory circuits;

an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and

a transmission line electrically coupling the interface circuit to the memory controller,

wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller, and wherein the single termination resistance has a value that is different from values specified by the resistance-setting commands received from the memory controller.

2. The apparatus of claim 1, wherein the single termination resistance is provided by an on-die termination (ODT) resistor.

3. The apparatus of claim 1, wherein the interface circuit selects a value of the single termination resistance from a look-up table.

4. The apparatus of claim 1, wherein the plurality of resistance-setting commands received from the memory controller comprises a first mode register set (MRS) command and a second MRS command.

5. The apparatus of claim 1, wherein a value of the single termination resistance during read operations is different from a value of the single termination resistance during write operations.

6. The apparatus of claim 1, wherein the plurality of memory circuits is a plurality of dynamic random access memory (DRAM) integrated circuits in a dual in-line memory module (DIMM).

7. The apparatus of claim 1, further comprising a resistor operable to provide the single termination resistance value, wherein the resistor is activated in response to a resistance-setting command issued by the interface circuit.

8. A method for providing termination resistance in a memory module, the method comprising:

receiving a plurality of resistance-setting commands from a memory controller at an interface circuit, wherein the interface circuit is operable to communicate with a plurality of memory circuits and with the memory controller;

selecting a resistance value based on the received plurality of resistance-setting commands; and

terminating a transmission line between the interface circuit and the memory controller with a resistor of the selected resistance value, wherein the selected resistance value is different from the values specified by the resistance-setting commands.

9. The method of claim 8, wherein the selected resistance value is a value for an on-die termination (ODT) resistor.

10. The method of claim 8, wherein the selected resistance value is selected from a look-up table.

11. The method of claim 8, wherein the selected resistance value during read operations is different from the selected resistance value during write operations.

12. The method of claim 8, wherein the plurality of memory circuits is a plurality of dynamic random access memory (DRAM) integrated circuits in a dual in-line memory module (DIMM).

13. The method of claim 8, wherein the plurality of resistance-setting commands is a plurality of mode register set (MRS) commands.

14. An apparatus for providing termination resistance in a memory module, the apparatus comprising:

a first memory circuit having a first termination resistor with a selectable value;

a second memory circuit having a second termination resistor with a selectable value; and

an interface circuit operable to communicate with the first and the second memory circuits and a memory controller, wherein the interface circuit is operable to select a single value for the first and the second termination resistors that is chosen based on a plurality of resistance-setting commands received from the memory controller, wherein the single value selected by the interface circuit for the first and the second termination resistors is different from values indicated by the plurality of resistance-setting commands received from the memory controller.

15. The apparatus of claim 14, wherein the first and the second termination resistors are on-die termination (ODT) resistors.

16. The apparatus of claim 14, wherein the interface circuit selects a single value for the first and the second termination resistors from a look-up table.

17. The apparatus of claim 14, wherein the plurality of resistance-setting commands received from the memory controller comprises a first mode register set (MRS) command and a second MRS command.

18. The apparatus of claim 14, wherein values of the first and the second termination resistors during read operations are different from values of the first and the second termination resistors during write operations.

19. The apparatus of claim 14, wherein the first and the second memory circuits are dynamic random access memory (DRAM) integrated circuits in a dual in-line memory module (DIMM).

20. The apparatus of claim 14, wherein the first and second terminations resistors are activated in response to one or more resistance-setting commands issued by the interface circuit.