Method and system for audio CODEC voice ADC processing

• US 8,169,344 B2
• Filed: 04/28/2011
• Issued: 05/01/2012
• Est. Priority Date: 11/30/2006
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Kong, Hongwei, Chang, Li Fung
• Primary Examiner(s): LAUTURE, JOSEPH J
• Application Number:
  US13/096,290
• Publication Number:
  US 20110199242A1
• Time in Patent Office: 369 Days
• Field of Search: 341/155, 341/143, 341/118, 341/120, 455/226.2, 455/333, 455/552, 455/415, 455/567
• US Class Current: 341/56
• CPC Class Codes: H03M 3/496 Details of sampling arrangements or methods

Abstract

Methods and systems for audio CODEC voice ADC processing are disclosed. Aspects of one method may include using a decimating filter that may be enabled to generate 13 MHz, 9-level digital output signal from a 26 MHz, 3-level digital input signal. The 13 MHz, 9-level digital output signal may be processed for RF transmission, for audio output to an output device, and/or utilized for testing by a test fixture, for example. The 13 MHz, 9-level digital output signal may be further processed to generate a 6.5 MHz, 33-level digital signal. The 6.5 MHz, 33-level digital signal may be converted to an analog signal, and processed for audio output and/or testing. The 13 MHz, 9-level digital output signal may also be processed to generate a 40 KHz, 17-bit digital signal, which may be communicated to a test equipment or further processed for RF transmission.

Claims

1. One or more circuits, comprising:

an audio codec;

a digital signal processor (DSP) operatively coupled to the audio codec;

a second processor; and

a memory that is shared by at least the second processor and the DSP,

wherein the one or more circuits are configured to support multiple wireless communication protocols and multiple antennas,

wherein the one or more circuits are configured to support separate processing paths for at least a general audio path, a voice path and a polyphonic ringer path before mixing the supported, separate processing paths,

wherein the one or more circuits are configured to decimate a multi-level digital input signal by M, where M is an integer that is greater than or equal to 2, and

wherein the one or more circuits are configured to generate an output digital signal having a number of signal levels greater than the multi-level digital input signal by processing the decimated multi-level digital input signal.

2. The one or more circuits according to claim 1, wherein the multi-level digital input signal includes digital samples at a rate of 26 mega-samples per second.

3. The one or more circuits according to claim 1, wherein the multi-level digital input signal includes at least three signal levels.

4. The one or more circuits according to claim 1, wherein the output digital signal includes at least nine signal levels.

5. The one or more circuits according to claim 1, wherein the one or more circuits are configured to process the output digital signal for one or more of the following:

testing, audio output and RF transmission.

6. The one or more circuits according to claim 1, wherein the one or more circuits are configured to decimate the output digital signal by N, where N is an integer that is greater than or equal to 2.

7. The one or more circuits according to claim 1, wherein the one or more circuits support one or more of the following:

Bluetooth, WCDMA, HSDPA, GSM, GPRS and EDGE.

8. The one or more circuits according to claim 1, wherein the one or more circuits are configured to convert a signal rate of the multi-level input digital signal, and wherein the converted signal rate is converted to an analog signal for communication to one or more of the following:

an output device and a test fixture.

9. The one or more circuits according to claim 1, wherein the one or more circuits are operatively coupled to a Bluetooth subsystem and to one or more of the following:

a WCDMA subsystem and a GSM subsystem.

10. The baseband processor one or more circuits according to claim 1, wherein the second processor comprises an ARM processor, or wherein the DSP comprises a speech codec.

11. The one or more circuits according to claim 1, wherein the one or more circuits include one or more of the following:

a graphics accelerator, an MPEG accelerator and a JPEG accelerator.

12. The one or more circuits according to claim 1, wherein the one or more circuits are operatively coupled to an input device and to an output device, wherein the input device includes one or more of the following:

a microphone, an auxiliary microphone, a camera, a video recorder and a keypad, and wherein the output device includes one or more of the following;

a speaker, a speakerphone, stereo speakers, headphones and a display.

13. The one or more circuits according to claim 1, wherein the audio codec is configured to support a plurality of digital audio inputs, wherein the audio codec is configured to support digital audio signals at a plurality of sampling rates.

14. A wireless communication system, comprising:

a one or more circuits that include an audio codec, a digital signal processor (DSP), a core second processor and a memory, wherein the DSP is operatively coupled to the audio codec, wherein the memory is shared by at least the second processor and the DSP,

wherein the one or more circuits are configured to support multiple wireless communication protocols and multiple antennas,

wherein the one or more circuits are configured to support separate processing paths for at least a general audio path, a voice path and a polyphonic ringer path before mixing the supported, separate processing paths,

wherein the one or more circuits are configured to decimate a multi-level digital input signal by M, where M is an integer that is greater than or equal to 2, and

wherein the one or more circuits are configured to generate an output digital signal having a number of signal levels greater than the multi-level digital input signal by processing the decimated multi-level digital input signal.

15. The one or more circuits according to claim 14, wherein the Bluetooth subsystem comprises a Bluetooth radio that is integrated on a single chip.

16. The system according to claim 15, wherein the one or more circuits are operatively coupled to a Bluetooth subsystem and to one or more of the following:

a WCDMA subsystem and a GSM subsystem.

17. The system according to claim 15, wherein the one or more circuits support one or more of the following:

Bluetooth, WCDMA, HSDPA, GSM, GPRS and EDGE.

18. The system according to claim 15, wherein the Bluetooth subsystem comprises a Bluetooth radio that is integrated on a single chip, wherein the second processor comprises an ARM processor, or wherein the DSP comprises a speech codec.

19. The system according to claim 15,

wherein the one or more circuits include one or more of the following:

a graphics accelerator, an MPEG accelerator and a JPEG accelerator, or

wherein the one or more circuits are operatively coupled to an input device and to an output device, wherein the input device includes one or more of the following;

a microphone, an auxiliary microphone, a camera, a video recorder and a keypad, and wherein the output device includes one or more of the following;

a speaker, a speakerphone, stereo speakers, headphones and a display.

20. A mobile wireless communication device, comprising:

one or more circuits that include an audio codec, a digital signal processor (DSP), a second processor and a memory, wherein the DSP is operatively coupled to the audio codec, wherein the memory is shared by at least the second processor and the DSP,

wherein the one or more circuits are configured to support multiple wireless communication protocols and multiple antennas,

wherein the one or more circuits are configured to support separate processing paths for at least a general audio path, a voice path and a polyphonic ringer path before mixing the supported, separate processing paths,

wherein the one or more circuits are configured to decimate a multi-level digital input signal by M, where M is an integer that is greater than or equal to 2,

wherein the one or more circuits are configured to generate an output digital signal having a number of signal levels greater than the multi-level digital input signal by processing the decimated multi-level digital input signal, and

wherein the supports one or more circuits support at least two of the following;

Bluetooth, WCDMA, HSDPA, GSM, GPRS and EDGE.