Parallel data processing apparatus

• US 8,169,440 B2
• Filed: 05/29/2007
• Issued: 05/01/2012
• Est. Priority Date: 04/09/1999
• Status: Expired due to Fees

• Current Assignee: Rambus Inc.
• Original Assignee: Rambus Inc.
• Inventors: Stuttard, Dave, Williams, Dave, O'Dea, Eamon, Faulds, Gordon, Rhoades, John, Cameron, Ken, Atkin, Phil, Winser, Paul, McConnell, Ray, Day, Tim, Greer, Trey, David, Russell
• Primary Examiner(s): Richer, Aaron M
• Assistant Examiner(s): CRADDOCK, ROBERT J
• Application Number:
  US11/754,901
• Publication Number:
  US 20080028184A1
• Time in Patent Office: 1,799 Days
• Field of Search: 345/622, 345/505, 345/519, 712 10- 12
• US Class Current: 345/505
• CPC Class Codes: G06F 15/8007 single instruction multiple data [SIMD] multiprocessors
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3001 Arithmetic instructions
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3851 from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3887 controlled by a single instruction for multiple data lanes [SIMD]
• CPC Class Codes: G06T 1/20 Processor architectures; Processor configuration, e.g. pipelining

Abstract

A method of processing data relating to geometrical primitives is disclosed. Each of the primitives has a plurality of vertices. The method uses a plurality of processing elements in parallel with one another, and comprises assigning respective vertex data to the processing elements, on each processing element, and in parallel with one another, performing at least one processing step on vertex data to produce processed vertex data, and transferring processed vertex data between processing elements so as to assemble primitive data.

Claims

1. A method of processing data relating to geometrical primitives, each of which has a plurality of vertices, and comprising the steps of:

using a plurality of single instruction multiple data (SIMD) processing arrays to process the data, wherein each SIMD array comprises a plurality of processing elements configured to process data in parallel with each another;

wherein processing the data comprises,

assigning respective vertex data to the processing elements, and

on each processing element, performing at least one processing step on vertex data to produce processed vertex data,

using a linear expression evaluator (LEE) circuit, which is coupled to each SIMD processing array in the plurality of SIMD processing arrays, to evaluate a linear expression,

wherein the linear expression is of the form ax_i+by_i+c, wherein x_i and y_i are variables associated with pixels, and a, b and c are coefficients,

wherein the LEE is coupled to each SIMD processing array through a feedback bus, which enables data to flow from each processing element in the SIMD to the LEE and back to processing element, and

wherein the feedback bus includes a feedback buffer (FBB) to store the coefficients a, b and c.

2. A method as claimed in claim 1, wherein at least one processing element stores data relating to at least one of the geometrical primitives.

3. A method as claimed in claim 1, wherein each processing element stores data relating to at least on geometrical primitive.

4. A method as claimed in claim 1, wherein the processed vertex data is transferred between processing elements using direct inter-processing element connections.

5. A method as claimed in claim 1, wherein the processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.

6. The method of claim 1, wherein using the plurality of SIMD processing arrays involves using a binning circuit, which is coupled to each array of SIMD processing units, to facilitate sorting processed vertex data from the processing elements in each SIMD processing array.

7. A graphical data processing apparatus comprising:

a plurality of single instruction multiple data (SIMD) processing arrays, wherein each SIMD array comprises a plurality of processing elements configured in parallel with one another such that each SIMD array is operable to process a plurality of instruction threads in parallel with one another, and

a controller operable to assign respective vertex data to the processing elements, which vertex data relates to geometrical primitives, wherein each processing element is operable to perform at least one processing step on vertex data to produce processed vertex data,

wherein the controller is operable to assemble primitive data by causing processed image data to be transferred between processing elements; and

a linear expression evaluator (LEE) circuit coupled to each SIMD processing array in the plurality of SIMD processing arrays,

wherein the LEE is configured to evaluate a linear expression of the form ax_i+by_i+c, wherein x_i and y_i are variables associated with pixels, and a, b and c are coefficients,

wherein the LEE is coupled to each SIMD processing array through a feedback bus, which enables data to flow from each processing element in the SIMD to the LEE and back to processing element, and

wherein the feedback bus includes a feedback buffer (FBB) to store the coefficients a, b and c.

8. An apparatus as claimed in claim 7, wherein the controller operable to cause at least one processing element to store data relating to at least one of the geometrical primitives.

9. An apparatus as claimed in claim 7, wherein the controller is operable to cause each processing element to store data relating to at least one geometrical primitive.

10. An apparatus as claimed in claim 7, comprising direct inter-processing element connections for transfer of processed vertex data therebetween.

11. An apparatus as claimed in claim 7, wherein the processing step is chosen from a group including transformation to screen space, geometry, lighting and shading processing steps.

12. The apparatus of claim 7, further comprising a binning circuit, which is coupled to each array of SIMD processing units, to facilitate sorting processed vertex data from the processing elements in each SIMD processing array.