Reliable data storage in analog memory cells subjected to long retention periods

• US 8,169,825 B1
• Filed: 09/01/2009
• Issued: 05/01/2012
• Est. Priority Date: 09/02/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Anobit Technologies, Ltd. (Apple Inc.)
• Inventors: Shalvi, Ofir, Sommer, Naftali, Rotbard, Barak, Golov, Oren, Anholt, Micha, Perlmutter, Uri
• Primary Examiner(s): Luu, Pho M
• Assistant Examiner(s): Bui, Thao
• Application Number:
  US12/551,567
• Time in Patent Office: 973 Days
• Field of Search: 365/189.09, 365/189.11, 365/226, 365/228, 365/229, 365/185.09, 365/227, 365/189.2, 365/189.17
• US Class Current: 365/185.09
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0033 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2211/5641 Multilevel memory having cells with different number of storage levels
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS

Abstract

A method for data storage in a non-volatile memory includes storing data in the non-volatile memory using a first storage configuration while the non-volatile memory is supplied with electrical power. After storing the data, an indication is accepted, indicating that shut-off of the electrical power is imminent. Responsively to the indication and before the shut-off, at least some of the data is re-programmed in the non-volatile memory using a second storage configuration.

Claims

1. A method for data storage in a non-volatile memory, the method comprising:

while the non-volatile memory is supplied with electrical power, storing data in the non-volatile memory using a first storage configuration;

after storing the data, accepting an indication that shut-off of the electrical power is imminent; and

responsively to the indication and before the shut-off, re-programming at least some of the data in the non-volatile memory using a second storage configuration,

wherein the first storage configuration has a first data retention period, and wherein the second storage configuration has a second data retention period, longer than the first data retention period.

2. The method according to claim 1, wherein the electrical power is supplied from a host system, and wherein accepting the indication comprises receiving from the host system a notification that the shut-off is imminent.

3. The method according to claim 1, wherein the non-volatile memory is comprised in a storage device, which is removably connected to a host system and which receives the electrical power from the host system, and wherein the shut-off is caused by removal of the storage device from the host system.

4. The method according to claim 3, wherein the storage device comprises a Solid-State Disk (SSD).

5. The method according to claim 1, wherein the non-volatile memory comprises a plurality of analog memory cells, wherein storing the data using the first storage configuration comprises programming a first group of the analog memory cells using a first number of programming states, and wherein re-programming the at least some of the data comprises programming a second group of the memory cells using a second number of the programming states, which is less than the first number.

6. The method according to claim 1, wherein storing the data using the first storage configuration comprises encoding the stored data using a first Error Correction Code (ECC) having a first error correction capability, and wherein re-programming the at least some of the data comprises encoding the at least some of the data using a second Error Correction Code (ECC) having a second error correction capability, which is higher than the first error correction capability.

7. The method according to claim 1, wherein the non-volatile memory comprises a plurality of analog memory cells, wherein storing the data using the first storage configuration comprises programming a first group of the memory cells using a first sequence of programming pulses having a first programming step size, and wherein re-programming the at least some of the data comprises programming a second group of the memory cells using a second sequence of the programming pulses having a second programming step size, which is smaller than the first programming step size.

8. The method according to claim 1, wherein storing the data using the first storage configuration comprises pre-equalizing the stored data using a first pre-equalization scheme having a first interference cancellation level, and wherein re-programming the at least some of the data comprises pre-equalizing the at least some of the data using a second pre-equalization scheme having a second interference cancellation level, which is better than the first interference cancellation level.

9. The method according to claim 8, wherein storing the data using the first storage configuration comprises refraining from pre-equalizing the stored data.

10. The method according to claim 1, wherein the non-volatile memory comprises a plurality of analog memory cells, wherein storing the data using the first storage configuration comprises programming a first group of the memory cells using one or more first voltages, and wherein re-programming the at least some of the data comprises programming a second group of the memory cells using one or more second voltages, at least one of which is higher than a respective first voltage.

11. The method according to claim 10, wherein the voltages comprise at least one voltage type selected from a group of types consisting of programming voltages and pass voltages.

12. The method according to claim 1, wherein the non-volatile memory comprises a plurality of analog memory cells, wherein storing the data using the first storage configuration comprises programming a first group of the analog memory cells using first programming states that occupy a first range, and wherein re-programming the at least some of the data comprises programming a second group of the memory cells using second programming states that occupy a second range, which is wider than the first range.

13. The method according to claim 1, and comprising, responsively to determining that the electrical power has been restored following the shut-off, restoring the re-programmed data in the non-volatile memory from the second storage configuration to the first storage configuration.

14. The method according to claim 13, wherein restoring the re-programmed data comprises reading the re-programmed data using a first read operation having a first reading accuracy, which is higher than a second reading accuracy of a second read operation used for reading the data stored using the first storage configuration.

15. The method according to claim 14, wherein the non-volatile memory comprises a plurality of analog memory cells, and wherein reading the re-programmed data comprises reading the memory cells using a first number of read thresholds, which is higher than a second number of the read thresholds used in the second read operation.

16. The method according to claim 14, wherein reading the re-programmed data comprises applying to the re-programmed data a first signal processing scheme having a first performance level, which is higher than a second performance level of a second signal processing scheme used in the second read operation.

17. The method according to claim 16, wherein applying the first signal processing scheme comprises applying a first Error Correction Code (ECC) decoding scheme having a first error correction capability, which is higher than a second error correction capability of a second ECC decoding scheme used in the second read operation.

18. The method according to claim 16, wherein applying the first signal processing scheme comprises applying a first interference cancellation scheme having a first interference cancellation level, which is higher than a second interference cancellation level of a second interference cancellation scheme used in the second read operation.

19. The method according to claim 14, wherein the second read operation operates on hard decoding metrics computed for the stored data, and wherein reading the re-programmed data comprises computing soft decoding metrics from the re-programmed data and decoding the re-programmed data using the soft decoding metrics.

20. The method according to claim 14, wherein the non-volatile memory comprises a plurality of analog memory cells, and wherein reading the re-programmed data comprises reading the memory cells using one or more first read voltages, at least one of which is higher than a respective second read voltage used in the second read operation.

21. The method according to claim 14, wherein the non-volatile memory comprises a plurality of analog memory cells, and wherein reading the re-programmed data comprises re-reading the memory cells a first number of times, which is larger than a second number of times the memory cells are read in the second read operation.

22. The method according to claim 13, and comprising storing known data in a part of the non-volatile memory before the shut-off, and assessing an impact of the shut-off on the re-programmed data by reading the part of the non-volatile memory after the electrical power has been restored.

23. The method according to claim 13, and comprising outputting a notification, which indicates that access speed to the non-volatile memory is temporarily degraded during a time period in which the re-programmed data is restored from the second storage configuration to the first storage configuration.

24. The method according to claim 1, wherein accepting the indication comprises sensing a loss of the electrical power.

25. The method according to claim 1, wherein re-programming the at least some of the data comprises switching to a temporary power source responsively to the indication, and re-programming the at least some of the data while drawing energy from the temporary power source.

26. The method according to claim 1, wherein the non-volatile memory comprises a plurality of analog memory cells, and comprising:

identifying a group of the memory cells that are expected to distort the re-programmed data during the shut-off;

storing information related to the identified memory cells; and

recovering the data re-programmed in the identified memory cells using the stored information.

27. A method for data storage in a non-volatile memory, the method comprising:

while the non-volatile memory is supplied with electrical power, storing data in the non-volatile memory using a first storage configuration;

after storing the data, accepting an indication that shut-off of the electrical power is imminent; and

responsively to the indication and before the shut-off, re-programming at least some of the data in the non-volatile memory using a second storage configuration,

wherein the non-volatile memory is partitioned into a normal storage area and an over-provisioning storage area, and wherein re-programming the at least some of the data comprises storing a first part of the re-programmed data in the normal storage area, and a second part of the re-programmed data in the over-provisioning storage area.

28. The method according to claim 27, and comprising making an attempt to recover the re-programmed data using only the first part, and, responsively to a failure of the attempt, recovering the re-programmed data using both the first and the second parts.

29. Apparatus for data storage, comprising:

an interface, which is coupled to communicate with a non-volatile memory; and

circuitry, which is coupled to store data in the non-volatile memory using a first storage configuration while the non-volatile memory is supplied with electrical power, to accept, after storing the data, an indication that shut-off of the electrical power is imminent, and, responsively to the indication and before the shut-off, to re-program at least some of the data in the non-volatile memory using a second storage configuration,

wherein the first storage configuration has a first data retention period, and wherein the second storage configuration has a second data retention period, longer than the first data retention period.

30. The apparatus according to claim 29, wherein the electrical power is supplied from a host system, and wherein the circuitry is coupled to receive from the host system a notification that the shut-off is imminent.

31. The apparatus according to claim 29, wherein the non-volatile memory is comprised in a storage device, which is removably connected to a host system and which receives the electrical power from the host system, and wherein the shut-off is caused by removal of the storage device from the host system.

32. The apparatus according to claim 31, wherein the storage device comprises a Solid-State Disk (SSD).

33. The apparatus according to claim 29, wherein the circuitry is coupled to restore the re-programmed data in the non-volatile memory from the second storage configuration to the first storage configuration responsively to determining that the electrical power has been restored following the shut-off.

34. The apparatus according to claim 33, wherein the circuitry is coupled to restore the re-programmed data by reading the re-programmed data using a first read operation having a first reading accuracy, which is higher than a second reading accuracy of a second read operation used for reading the data stored using the first storage configuration.