Memory system and method with serial and parallel modes

• US 8,169,849 B2
• Filed: 03/27/2009
• Issued: 05/01/2012
• Est. Priority Date: 12/12/2006
• Status: Active Grant

• Current Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Original Assignee: Mosaid Technologies Incorporated (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: Oh, HakJune, Kim, Jin-Ki, Pyeon, Hong Pyeon
• Primary Examiner(s): Dinh, Son
• Assistant Examiner(s): NGUYEN, NAM THANH
• Application Number:
  US12/412,968
• Publication Number:
  US 20090185442A1
• Time in Patent Office: 1,131 Days
• Field of Search: 365/230.03, 365/230.02, 365/189.02, 365/185.11
• US Class Current: 365/230.03
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1075 for multiport memories each having random access ports and serial ports, e.g. video RAM
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

Methods and systems are provided that allow the method of access to one or more memory banks to be performed using serial access, or using parallel access. In serial mode, each link operates as an independent serial link. In contrast, during serial mode, the links operate in common as a parallel link. Where input and output controls are received independently for each link for serial mode, a single set of input and output controls is used in common by all of the links during parallel mode.

Claims

1. An apparatus for use with a memory system, the memory system having at least two memory banks, the apparatus comprising:

a first switch for switching, while in a serial mode of operation, an input of a plurality of inputs to a selected memory bank of the at least two memory banks, the input operating as a serial input while in the serial mode of operation;

a second switch for switching, while in a parallel mode of operation, a parallel input to a selected memory bank of the at least two memory banks, the plurality of inputs, while in a parallel mode of operation, constituting the parallel input.

2. The apparatus of claim 1 further comprising:

for each of said at least two memory banks, a respective multiplexer;

each multiplexer having a first input connected to an output of the first switch and having a second input connected to an output of the second switch, and having an output connected to the respective memory bank.

3. The apparatus of claim 2 further comprising:

for each multiplexer, a serial to parallel converter between the first switch and the first input of the multiplexer.

4. The apparatus of claim 3 further comprising:

a data width converter configured to produce a parallel input by converting between a parallel input having a data width equal to the number of inputs of said plurality of inputs to a parallel input having a data width for bank access.

5. The apparatus of claim 4 wherein the number of inputs is four and the data width for bank access is eight.

6. The apparatus of claim 1 further comprising:

a third switch for switching, while in the serial mode of operation, an output of a selected memory bank to an output of a plurality of outputs, the output operating as a serial output while in the serial mode of operation;

connections for connecting, while in the parallel mode of operation, an output of a selected memory bank to a parallel output, the plurality of outputs constituting, while in the parallel mode of operation, the parallel output.

7. The apparatus of claim 6 further comprising:

for each of said plurality of outputs, a respective multiplexer;

each multiplexer having a first input connected to an output of the third switch and having a second input connected to an output of a selected memory bank, and having an output connected to the respective output.

8. The apparatus of claim 7 wherein the number of outputs equals the number of memory banks such that the multiplexers include a respective multiplexer for each memory bank, the apparatus further comprising:

for each multiplexer, a parallel to serial to converter between the respective memory bank and the third switch.

9. The apparatus of claim 8 further comprising:

a data width converter configured to produce a parallel output by converting an output from a selected bank from a data width for bank access to a data width equal to the number of outputs of said plurality of outputs.

10. The apparatus of claim 9 wherein the number of inputs is four and the data width for bank access is eight.

11. The apparatus of claim 1 further comprising:

for each input, a respective link and bank controller;

each link and bank controller having a respective input of said plurality of inputs, a first input control and a first output control for use during serial operation of the corresponding input;

each link and bank controller having an input for receiving a data width control input common to all of the link and bank controllers;

for at least one link and bank controller;

a second input control input connected to the input control input of another link and bank controller, and a second output control input connected to the output control input of the another link and bank controller;

the at least one link and bank controller configured to operate as a function of control signals on the first input control and first output control during serial mode of operation, and to operate as a function of control signals on the second input control and the second output control during parallel mode of operation.

12. The method of claim 11 further comprising:

receiving, at a respective link and bank controller for each input, a data width control input common to all of the link and bank controllers;

for at least one link and bank controller;

during serial mode operation, operating the at least one link and bank controllers as a function of control signals on a first input control and a first output control of the respective at least one link and bank controller; and

during parallel mode operation, operating the at least one link and bank controllers as a function of control signals on a second input control of the respective link and bank controller connected to the input control input of another link and bank controller and a second output control input of the respective link and bank controller connected to the output control input of another link and bank controller.

13. The apparatus of claim 1 in combination with said at least two memory banks.

14. A method comprising:

switching, while in a serial mode of operation, an input of a plurality of inputs to a selected memory bank of at least two memory banks, the input operating as a serial input while in the serial mode of operation;

switching, while in a parallel mode of operation, a parallel input to a selected memory bank of the at least two memory banks;

while in the parallel mode of operation, using the plurality of inputs to form the parallel input.

15. The method of claim 14 further comprising:

while in the serial mode of operation, converting the input to a parallel format.

16. The method of claim 15 further comprising:

while in the parallel mode of operation, converting between a parallel input having a data width equal to the number of inputs of said plurality of inputs to a parallel input having a data width for bank access.

17. The method of claim 14 further comprising:

switching, while in the serial mode of operation, an output of a selected memory bank to an output of a plurality of outputs, the output operating as a serial output when in the serial mode of operation;

connecting, while in the parallel mode of operation, an output of a selected memory bank to a parallel output;

while in the parallel mode of operation, using the plurality of outputs to form the parallel output.

18. The method of claim 17 wherein,

the number of outputs equals the number of memory banks, and

switching, when in the serial mode of operation, the output of the selected memory bank to the output of the plurality of outputs further comprises converting the output of the selected memory bank from a parallel format to a serial format.

19. The method of claim 18 further comprising:

when in the parallel mode of operation, producing the parallel output by converting an output from the selected bank from a data width for bank access to a data width equal to the number of outputs of said plurality of outputs.