CPU transmission of unmodified packets

• US 8,170,019 B2
• Filed: 03/28/2005
• Issued: 05/01/2012
• Est. Priority Date: 11/30/2004
• Status: Expired due to Fees

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Anand, Anupam, Dull, John Jeffrey
• Primary Examiner(s): Pham, Chi
• Assistant Examiner(s): RIYAMI, ABDULLAH A
• Application Number:
  US11/090,143
• Publication Number:
  US 20060114895A1
• Time in Patent Office: 2,591 Days
• Field of Search: 370/299, 370/386, 370/392, 370/389, 370/390, 370/398, 370/401, 370/404, 370/412, 370/413, 370/414, 370/415, 370/416, 370/417, 370/418, 370/419, 370/420, 370/422, 370/423, 370/428, 370/429, 370/432, 370/473, 370/474
• US Class Current: 370/392
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 45/742 Route cache; Operation thereof
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3063 Pipelined operation

Abstract

A network device for processing packet. The network device includes an ingress module for performing switching functionality on an incoming packet, wherein the network device determines a destination port to which the incoming packet is to be transmitted. The network device also includes a CPU processing module for transmitting information between the network device and an external CPU. The external CPU transmits a formatted packet to the network device through the CPU processing module. The formatted packet includes module header and a data field. The ingress module uses information in a start field of the module header to determine that the incoming packet is a formatted packet and generates instructions for notifying other modules of the network device that the formatted packet is not to be modified by the network device and determines that the formatted packet is to be transmitted to a destination field in the formatted packet.

Claims

1. An apparatus, comprising:

a CPU processing module configured to receive a packet from an external CPU, wherein the received packet includes a header portion and a data portion, and wherein the header portion includes a field identifying the packet as a CPU formatted packet and a field indicating a local destination port determined by the external CPU;

an ingress module configured to receive the packet from the CPU processing module, identify the packet as a CPU formatted packet, and issue an operation code indicating the packet may not be modified during processing by the apparatus; and

an egress module configured to receive the packet from the ingress module and process the packet without modifying the packet;

wherein the egress module is configured to determine whether to drop the packet or to send the packet to the local destination port determined by the external CPU.

2. The apparatus of claim 1, wherein the ingress module further comprises a discard stage configured to determine whether to drop the packet.

3. The apparatus of claim 1, wherein the ingress module is configured to receive packets from the CPU processing module and at least one ingress port, and further comprises an arbiter configured to schedule access to the CPU processing module.

4. The apparatus of claim 3, wherein the arbiter is configured to issue at least one of a packet operation code, an instruction operation code or a refresh code.

5. The apparatus of claim 1, further comprising a memory management unit configured to apply resource accounting and aging logic to the received packet.

6. The apparatus of claim 5, wherein the egress module receives the packet from the ingress module by way of the memory management unit.

7. The apparatus of claim 1, wherein all table lookups and switching decisions are skipped in the egress module.

8. A computer implemented method for processing packets in a network device, comprising:

receiving an incoming packet from an external CPU, wherein the incoming packet includes a header portion and a data portion, and wherein the header portion includes a field identifying the packet as a CPU formatted packet and a field indicating a local destination port determined by the external CPU;

identifying the packet as a CPU formatted packet from the header portion and issuing an operation code for processing the packet, wherein the operation code indicates the packet may not be modified during processing; and

processing the packet to determine whether to drop the packet or to send the packet to the local destination port determined by the external CPU.

9. The computer implemented method of claim 8, wherein processing the packet to determine whether to drop the packet further comprises applying resource accounting and aging logic to the packet.

10. The computer implemented method of claim 8, wherein the packet is received at an ingress module.

11. The computer implemented method of claim 8, further comprising storing the packet in a memory while it is being processed.

12. The computer implemented method of claim 8, wherein the packet is sent to the destination port determined by the external CPU through an egress module.

13. A computer program product, embodied on a non-transitory machine-readable medium, comprising instructions operable to cause a programmable processor to:

receive an incoming packet from an external CPU, wherein the incoming packet includes a header portion and a data portion, and wherein the header portion includes a field identifying the packet as a CPU formatted packet and a field indicating a local destination port determined by the external CPU;

identify the packet as a CPU formatted packet from the header portion and issue an operation code for processing the packet that indicates the packet may not be modified during processing; and

process the packet to determine whether to drop the packet or to send the packet to the local destination port determined by the external CPU.

14. The computer program product of claim 13, wherein the instruction to process the packet to determine whether to drop the packet further comprises instructions to apply resource accounting and again logic to the packet.

15. The computer program product of claim 13, wherein the instruction to receive the packet comprises an instruction to receive the packet at an ingress module.

16. The computer program product of claim 13, further comprising an instruction to store the packet in a memory while it is being processed.

17. The computer program product of claim 13, wherein the instruction to send the packet to the destination port determined by the external CPU comprises an instruction to send the packet through an egress module.