Method, system, and apparatus for dynamic reconfiguration of resources

• US 8,171,121 B2
• Filed: 09/23/2008
• Issued: 05/01/2012
• Est. Priority Date: 12/13/2004
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ayyar, Mani, Delano, Eric, Schoinas, Ioannis T., Kumar, Akhilesh, Jayasimha, Jay, Vargas, Jose A.
• Primary Examiner(s): Alrobaye, Idriss N
• Application Number:
  US12/236,047
• Publication Number:
  US 20090019267A1
• Time in Patent Office: 1,316 Days
• Field of Search: None
• US Class Current: 709/221
• CPC Class Codes: G06F 13/00 Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units interface circuits for specific input/output devices G06F3/00 ; multiprogram control therefor G06F9/46; multiprocessor systems G06F15/16
• CPC Class Codes: G06F 13/24 using interrupt G06F13/32 takes precedence
• CPC Class Codes: G06F 13/4081 Live connection to bus, e.g. hot-plugging current or voltage limitation during live insertion H02H9/004
• CPC Class Codes: G06F 13/409 Mechanical coupling back panels H05K7/1438
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files
• CPC Class Codes: G06F 9/50 Allocation of resources, e.g. of the central processing unit [CPU]
• CPC Class Codes: G06F 9/5011 the resources being hardware resources other than CPUs, Servers and Terminals

Abstract

A dynamic reconfiguration to include on-line addition, deletion, and replacement of individual modules of to support dynamic partitioning of a system, interconnect (link) reconfiguration, memory RAS to allow migration and mirroring without OS intervention, dynamic memory reinterleaving, CPU and socket migration, and support for global shared memory across partitions is described. To facilitate the on-line addition or deletion, the firmware is able to quiesce and de-quiesce the domain of interest so that many system resources, such as routing tables and address decoders, can be updated in what essentially appears to be an atomic operation to the software layer above the firmware.

Claims

1. A method for on-line deletion of a processor node comprising:

requesting the removal of the processor node to an operating system through system management channels;

moving applications away from processors and memory being offlined with respect to the processor node that is requested for removal with the operating system;

moving interrupts away from the processor node and disabling interrupts to the processors being offlined with the operating system;

stopping prefetches and speculative accesses by removal of translation lookaside buffers (TLBs) to avoid errors due to references to memory that are mapped out by address decoder;

performing a quiesce operation to ensure that in-transit snoop operations are completed, wherein a quiesced state is a state where there are no protocol transactions in the full system or a subset thereof except those generated by firmware and/or service system processors;

removing the processor node that is requested for removal from one or more participant lists; and

generating a signal that the processor node that is requested for removal can be physically removed.

2. The method of claim 1, wherein moving applications away from processors and memory being offlined with respect to the processor node that is requested for removal is performed by an Operating System (OS).

3. (The method of claim 1, wherein the processor node may contain IA-32 or ITANIUM processors.