Bus interconnect device and a data processing apparatus including such a bus interconnect device
First Claim
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1. A data processing chip comprising:
- a bus interconnect device formed of a parallel plate waveguide comprising parallel plates, said parallel plates separated by a distance in a first dimension orthogonal to said plates, said plates extending in second and third dimensions, said second and third dimensions orthogonal to each other;
a plurality of at least three devices forming a plurality of functional blocks of the data processing chip that are coupled together by the bus interconnect device, each device being coupled into the parallel plate waveguide at a chosen location within one of the parallel plates, wherein the relative positioning of each device with respect to the other at least two devices is arbitrary in said second and third dimensions;
said plurality of at least three devices being arranged to communicate via radio frequency (RF) signals propagated through the parallel plate waveguide as waves radiated between the parallel plates in said second and third dimensions, allowing direct simultaneous communications between devices of said at least three devices, wherein;
the plurality of functional blocks includes an array of processing elements, the plurality of functional blocks being further coupled via a wired bus network,the parallel plate waveguide is useable for global communication among the array of processing elements, andthe wired bus network is useable for inter-neighbor communication between the processing elements.
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Abstract
A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus.
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Citations
13 Claims
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1. A data processing chip comprising:
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a bus interconnect device formed of a parallel plate waveguide comprising parallel plates, said parallel plates separated by a distance in a first dimension orthogonal to said plates, said plates extending in second and third dimensions, said second and third dimensions orthogonal to each other; a plurality of at least three devices forming a plurality of functional blocks of the data processing chip that are coupled together by the bus interconnect device, each device being coupled into the parallel plate waveguide at a chosen location within one of the parallel plates, wherein the relative positioning of each device with respect to the other at least two devices is arbitrary in said second and third dimensions; said plurality of at least three devices being arranged to communicate via radio frequency (RF) signals propagated through the parallel plate waveguide as waves radiated between the parallel plates in said second and third dimensions, allowing direct simultaneous communications between devices of said at least three devices, wherein; the plurality of functional blocks includes an array of processing elements, the plurality of functional blocks being further coupled via a wired bus network, the parallel plate waveguide is useable for global communication among the array of processing elements, and the wired bus network is useable for inter-neighbor communication between the processing elements. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A multi-chip module comprising a plurality of chips mounted on a substrate, the multi-chip module comprising:
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a bus interconnect device provided in the substrate and formed of a parallel plate waveguide comprising parallel plates, said parallel plates separated by a distance in a first dimension orthogonal to said plates, said plates extending in second and third dimensions, said second and third dimensions orthogonal to each other; a plurality of at least three devices forming a plurality of chips of the multi-chip module that are coupled together by the bus interconnect device, each device being coupled into the parallel plate waveguide at a chosen location within one of the parallel plates, wherein the relative positioning of each device with respect to the other at least two devices is arbitrary in said second and third dimensions; said plurality of at least three devices being arranged to communicate via radio frequency (RF) signals propagated through the parallel plate waveguide as waves radiated between the parallel plates in said second and third dimensions, allowing direct simultaneous communications between devices of said at least three devices, wherein; the plurality of chips includes an array of processing elements, the plurality of chips being further coupled via a wired bus network, the parallel plate waveguide is useable for global communication among the array of processing elements, and the wired bus network is useable for inter-neighbor communication between the processing elements. - View Dependent Claims (9, 10)
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11. A printed circuit board (PCB) for receiving a plurality of chips, the PCB comprising:
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a bus interconnect device formed of a parallel plate waveguide comprising parallel plates, said parallel plates separated by a distance in a first dimension orthogonal to said plates, said plates extending in second and third dimensions, said second and third dimensions orthogonal to each other; a plurality of at least three devices forming a plurality of chips received by the PCB and coupled together by the bus interconnect device, each device being coupled into the parallel plate waveguide at a chosen location within one of the parallel plates, wherein the relative positioning of each device with respect to the other at least two devices is arbitrary in said second and third dimensions; said plurality of at least three devices being arranged to communicate via radio frequency (RF) signals propagated through the parallel plate waveguide as waves radiated between the parallel plates in said second and third dimensions, allowing direct simultaneous communications between devices of said at least three devices, wherein; the plurality of chips includes an array of processing elements, the plurality of chips being further coupled via a wired bus network, the parallel plate waveguide is useable for global communication among the array of processing elements, and the wired bus network is useable for inter-neighbor communication between the processing elements. - View Dependent Claims (12, 13)
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Specification
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Current AssigneeArm Ltd. (United Kingdom) (SoftBank Group Corp.)
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Original AssigneeArm Ltd. (United Kingdom) (SoftBank Group Corp.)
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InventorsBruce, Alistair Crone, Tune, Andrew David
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Primary Examiner(s)Zaman, Faisal M
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Application NumberUS12/309,740Publication NumberTime in Patent Office2,097 DaysField of Search710/100, 710/106, 710/301, 333/113, 385/129US Class Current710/100CPC Class CodesH01P 3/02 with two longitudinal condu...
