Intelligent solid-state non-volatile memory device (NVMD) system with multi-level caching of multiple channels

• US 8,171,204 B2
• Filed: 05/05/2008
• Issued: 05/01/2012
• Est. Priority Date: 01/06/2000
• Status: Expired due to Fees

• Current Assignee: Super Talent Technology, Corporation
• Original Assignee: Super Talent Electronics, Inc.
• Inventors: Chow, David Q., Yu, Frank, Lee, Charles C., Ma, Abraham C., Shen, Ming-Shiang
• Primary Examiner(s): PATEL, HETUL B
• Application Number:
  US12/115,128
• Publication Number:
  US 20080235443A1
• Time in Patent Office: 1,457 Days
• Field of Search: None
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0851 Cache with interleaved addressing
• CPC Class Codes: G06F 12/0866 for peripheral storage systems, e.g. disk cache
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 12/1045 associated with a data cache
• CPC Class Codes: G06F 12/1416 by checking the object accessibility, e.g. type of access defined by the memory independently of subject rights G06F12/1458 takes precedence
• CPC Class Codes: G06F 21/32 using biometric data, e.g. fingerprints, iris scans or voiceprints
• CPC Class Codes: G06F 21/78 to assure secure storage of data address-based protection against unauthorised use of memory G06F12/14; record carriers for use with machines and with at least a part designed to carry digital markings G06K19/00
• CPC Class Codes: G06F 21/79 in semiconductor storage media, e.g. directly-addressable memories
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 3/0664 at device level, e.g. emulation of a storage device or system
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A flash memory system stores blocks of data in Non-Volatile Memory Devices (NVMD) that are addressed by a logical block address (LBA). The LBA is remapped for wear-leveling and bad-block relocation by the NVMD. The NVMD are interleaved in channels that are accessed by a NVMD controller. The NVMD controller has a controller cache that caches blocks stored in NVMD in that channel, while the NVMD also contain high-speed cache. The multiple levels of caching reduce access latency. Power is managed in multiple levels by a power controller in the NVMD controller that sets power policies for power managers inside the NVMD. Multiple NVMD controllers in the flash system may each controller many channels of NVMD. The flash system with NVMD may include a fingerprint reader for security.

Claims

1. A Non-Volatile Memory Device (NVMD) comprising:

a host-device interface for receiving commands from a host over a host bus;

a bridge, coupled to the host-device interface, for converting requests from the host into concurrent requests;

a traffic controller and dispatcher, coupled to the bridge, receiving the concurrent requests, for dispatching the concurrent requests over an internal bus;

a plurality of NVMD branches, each NVMD branch coupled to the internal bus to receive one of the concurrent requests from the traffic controller and dispatcher;

wherein each NVMD branch of the plurality of NVMD branches further comprises;

a NVMD controller, coupled to the internal bus, having control logic and a flash channel interface; and

a NVMD memory;

wherein multiple NVMD branches are accessed concurrently in parallel by the concurrent requests;

wherein the NVMD is a single chip integrated onto a single substrate of silicon;

wherein the NVMD memory in each of the NVMD branches comprises;

a memory interface coupled to the flash channel interface;

a non-volatile memory array for storing blocks of data;

a block address manager, for receiving a logical block address (LBA) from the traffic controller and dispatcher, for mapping the LBA to a physical block address (PBA) within a non-volatile memory array in the NVMD;

wherein each NVMD branch of the plurality of NVMD branches further comprises;

a NVMD controller, coupled to the internal bus, having control logic and a plurality of flash channel interfaces;

wherein each of the plurality of flash channel interfaces is coupled to a NVMD memory;

whereby multiple NVMD memory are coupled to each NVMD controller;

wherein the NVMD controller further comprises;

a page buffer;

an address correlation page usage memory (ACPUM);

a partial logical-to-physical address and page usage information (PLTPPUI) tracking table;

a wear leveling counter and bad block indicator (WL/BB) tracking table; and

wherein the plurality NVMD memory include a reserved area for a plurality of first physical blocks and a plurality of second physical blocks, the first physical blocks referenced by a plurality of first special logical addresses while the second physical blocks referenced by a plurality of second special logical addresses;

wherein the plurality of first physical blocks is configured for storing the PLTPPUI tracking table and the plurality of second physical blocks for storing the WL/BB tracking table;

wherein the ACPUM is configured to keep one set, corresponding to a set number, from the PLTPPUI tracking table;

wherein the PLTPPUI tracking table is configured to hold correlations between the first special logical addresses and the first physical blocks;

wherein the WL/BB tracking table is configured to hold correlations between the second special logical addresses and the second physical blocks,

whereby requests from the host are dispatched to multiple NVMD branches.

2. The NVMD of claim 1 wherein the non-volatile memory in the NVMD memory comprises a flash memory, a phase-change memory, ferroelectric random-access memory (FRAM), Magnetoresistive RAM (MRAM), Memristor, PRAM, SONOS, Resistive RAM (RRAM), Racetrack memory, or nano RAM (NRAM).

3. The NVMD of claim 2 wherein access to the NVMD are address-interleaved in a dual-channel arrangement.

4. The NVMD of claim 1 wherein the NVMD controller further comprises:

a controller cache for storing blocks of data for storing in the NVMD memory.

5. The NVMD of claim 4 wherein the NVMD memory further comprises:

a high-speed cache for buffering a block of data for storage in the NVMD memory array,

wherein blocks are cached at two levels, in the NVMD controller and the NVMD memory, and are cached at two levels in each of the multiple NVMD branches.

6. The NVMD of claim 1 wherein the NVMD controller further comprises:

a controller power manager for setting power management policies for the NVMD memory.

7. The NVMD of claim 6 wherein the NVMD memory further comprises:

a local power manager, in the NVMD memory, for reducing power consumed by the NVMD memory in response to power management policies from the controller power manager;

wherein power is managed at two levels, in the NVMD controller and the NVMD memory, and power is managed at two levels in each of the multiple NVMD branches.

8. The NVMD of claim 1 further comprising:

a source clock for generating a clock for the internal bus;

a source synchronous interface, on each of the plurality of NVMD, for synchronizing transfers over the internal bus.

9. The NVMD of claim 1 wherein the ACPUM comprises a plurality of entries, each of the entries corresponding to a physical block number and page usage information of all pages of the physical block number.

10. The NVMD of claim 1 wherein the non-volatile memory in the NVMD memory array comprises a flash memory;

further comprising;

a fingerprint sensor for scanning a fingerprint for verification by the NVMD to enable the host-device interface to send data over the host bus.

11. A storage system comprising:

a connector to a host system, the connector having a host bus;

a host-device interface, coupled to the connector, for interfacing to the host using a host protocol;

a bridge, coupled to the host-device interface, for protocol conversion and handshaking;

a traffic controller and dispatcher, coupled to the bridge and to an internal bus, for dispatching concurrent requests over the host bus for concurrent operations;

a first Non-Volatile Memory Device (NVMD) branch having a first NVMD controller coupled to the internal bus and a first NVMD;

a second NVMD branch having a second NVMD controller coupled to the internal bus and a second NVMD;

wherein the first and second NVMD controller each comprise;

a logic circuit for interfacing to the internal bus;

a flash channel interface for channeling flash commands generated in response to one of the concurrent requests;

a page buffer;

an address correlation page usage memory (ACPUM);

a partial logical-to-physical address and page usage information (PLTPPUI) tracking table;

a wear leveling counter and bad block indicator (WL/BB) tracking table;

wherein the first and second NVMD each comprise;

a memory interface, coupled to the flash channel interface, for processing the flash commands; and

a non-volatile memory array for storing blocks of data in response to the flash commands received by the memory interface;

wherein the non-volatile memory array includes a reserved area for a plurality of first physical blocks and a plurality of second physical blocks, the first physical blocks referenced by a plurality of first special logical addresses while the second physical blocks referenced by a plurality of second special logical addresses;

wherein the plurality of first physical blocks is configured for storing the PLTPPUI tracking table and the plurality of second physical blocks for storing the WL/BB tracking table;

wherein the ACPUM is configured to keep one set, corresponding to a set number, from the PLTPPUI tracking table;

wherein the PLTPPUI tracking table is configured to hold correlations between the first special logical addresses and the first physical blocks;

wherein the WL/BB tracking table is configured to hold correlations between the second special logical addresses and the second physical blocks,

wherein concurrent requests are dispatched to the first and second NVMD branches.

12. The storage system of claim 11 wherein the first and second NVMD controller each further comprise:

a controller cache for caching blocks of data for the non-volatile memory array;

wherein the first and second NVMD each further comprise;

a high-speed cache for buffering blocks for storage into the non-volatile memory array,

whereby multi-level caching is performed.

13. The storage system of claim 11 wherein the first and second NVMD controller each further comprise:

a president controller for setting one or more policies for channels of memory;

wherein the policies control power management, wear-leveling, bad block management or replacement for one or more channels of memory;

wherein the first and second NVMD each further comprise;

a governor controller for implementing at least one of the policies by reducing power consumption or re-mapping blocks in the non-volatile memory array and the memory interface,

whereby multi-level power management wear-leveling, bad block management or replacement is performed.

14. The storage system of claim 13 further comprising:

a third NVMD branch having a third NVMD controller coupled to the internal bus and a third NVMD.

15. The storage system of claim 11 wherein the first NVMD controller has a first memory interface flash channel interface coupled to the first NVMD and a second flash channel interface coupled to a concurrent channel NVMD;

wherein the second NVMD controller has a third memory interface flash channel interface coupled to the second NVMD and a fourth flash channel interface coupled to a second concurrent channel NVMD.

16. The storage system of claim 15 wherein the first NVMD controller interleaves addresses to the first NVMD and to the concurrent channel NVMD;

wherein the second NVMD controller interleaves addresses to the second NVMD and to the second concurrent channel NVMD,

whereby addresses are interleaved to concurrent channel NVMD.