Cache architecture with distributed state bits

• US 8,171,220 B2
• Filed: 04/24/2009
• Issued: 05/01/2012
• Est. Priority Date: 04/24/2009
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Balakrishnan, Ganesh, Krishna, Anil
• Primary Examiner(s): Dinh, Son
• Application Number:
  US12/429,586
• Publication Number:
  US 20100275044A1
• Time in Patent Office: 1,103 Days
• Field of Search: 711/118, 711/160, 711/136, 711/3
• US Class Current: 711/118
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3225 of memory devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0817 using directory methods
• CPC Class Codes: G06F 12/0864 using pseudo-associative means, e.g. set-associative or hashing
• CPC Class Codes: G06F 12/126 with special data handling, e.g. priority of data or instructions, handling errors or pinning
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Embodiments that that distribute replacement policy bits and operate the bits in cache memories, such as non-uniform cache access (NUCA) caches, are contemplated. An embodiment may comprise a computing device, such as a computer having multiple processors or multiple cores, which has cache memory elements coupled with the multiple processors or cores. The cache memory device may track usage of cache lines by using a number of bits. For example, a controller of the cache memory may manipulate bits as part of a pseudo least recently used (LRU) system. Some of the bits may be in a centralized area of the cache. Other bits of the pseudo LRU system may be distributed across the cache. Distributing the bits across the cache may enable the system to conserve additional power by turning off the distributed bits.

Claims

1. A method, comprising:

enabling state bits of a pseudo least recently used (LRU) scheme of a cache memory device, wherein the state bits comprise root-node bits and lower-node bits for cache lines of the cache memory device, wherein further the lower-node bits are distributed in a plurality of structures of the cache memory device;

disabling bits of a data structure of the cache memory device to reduce power consumption; and

disabling state bits associated with the data structure, wherein the disabling the state bits comprises switching a plurality of the lower-node bits associated with the data structure.

2. The method of claim 1, wherein the enabling the state bits comprise enabling state bits for cache lines arranged into ways and sets.

3. The method of claim 2, wherein the disabling bits of the data array of the cache memory device comprises turning off data bits of a bank of a non-uniform cache access (NUCA) cache of a computing device.

4. The method of claim 1, wherein the root-node bits are stored in a centralized structure, separate from the lower-node bits.

5. The method of claim 1, wherein the root-node bits are distributed with the lower-node bits in the plurality of structures.

6. An apparatus, comprising:

a plurality of decentralized arrays of a cache memory, wherein state bits of a pseudo least recently used (LRU) scheme for the cache memory comprise root-node bits and lower-node bits, wherein further the lower-node bits are stored in the plurality of decentralized arrays; and

a cache controller to turn off the lower-node bits to conserve power.

7. The apparatus of claim 6, further comprising a power management module to turn off portions of the cache memory to conserve power.

8. The apparatus of claim 6, wherein root-node bits are stored in a centralized array of the cache memory, wherein further the centralized array comprises validity bits and coherency bits.

9. The apparatus of claim 8, wherein the cache memory is configured to apply power to the centralized array while some of the decentralized arrays are turned off, wherein further the centralized array comprises higher-node bits.

10. The apparatus of claim 6, wherein root-node bits are stored in the decentralized arrays with the lower-node bits.

11. The apparatus of claim 6, wherein the cache memory comprises a uniform cache access (UCA) cache.

12. The apparatus of claim 6, wherein the cache memory comprises an L3 non-uniform cache access (NUCA) cache module and the cache controller comprises a state machine.

13. The apparatus of claim 12, wherein the cache controller is arranged to turn off banks of the ways and turn off validity bits, coherency bits, and tag bits associated with the ways.

14. The apparatus of claim 12, wherein the cache controller is arranged to turn off banks of the ways and leave at least one of validity bits, coherency bits, and tag bits of the ways enabled, wherein further the root-node bits and lower-node bits comprise bits of a pseudo LRU tree.

15. A system comprising:

a plurality of processors;

a plurality of banks of a cache memory device coupled to the plurality of processors, wherein the cache memory device comprises a plurality of decentralized arrays; and

a cache controller to set state bits of a pseudo least recently used (LRU) scheme for the plurality of banks, wherein the state bits comprise root-node bits and lower-node bits, wherein further the lower-node bits are stored in the plurality of decentralized arrays, wherein further the cache controller is configured to turn off at a portion of the plurality of decentralized arrays to conserve power.

16. The system of claim 15, wherein the cache memory device comprises at least one centralized array to store root-node bits.

17. The system of claim 16, wherein the centralized array remains powered while some of the decentralized arrays are turned off.

18. The system of claim 15, wherein root-node bits are stored in the decentralized arrays with the lower-node bits.

19. The system of claim 18, wherein the decentralized arrays comprise tag information for data arrays.

20. The system of claim 19, wherein the tag information comprises at least one of validity bits and coherency bits, wherein further the cache memory device comprises a non-uniform cache access (NUCA) cache with horizontally-striped ways.