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Cache architecture with distributed state bits

  • US 8,171,220 B2
  • Filed: 04/24/2009
  • Issued: 05/01/2012
  • Est. Priority Date: 04/24/2009
  • Status: Expired due to Fees
First Claim
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1. A method, comprising:

  • enabling state bits of a pseudo least recently used (LRU) scheme of a cache memory device, wherein the state bits comprise root-node bits and lower-node bits for cache lines of the cache memory device, wherein further the lower-node bits are distributed in a plurality of structures of the cache memory device;

    disabling bits of a data structure of the cache memory device to reduce power consumption; and

    disabling state bits associated with the data structure, wherein the disabling the state bits comprises switching a plurality of the lower-node bits associated with the data structure.

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