D-cache line use history based done bit based on successful prefetchable counter
First Claim
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1. A method of providing history based done logic for a D-cache, the method comprising:
- receiving a D-cache line in an L2 cache;
determining if the D-cache line is unprefetchable;
aging the D-cache line without a delay if the D-cache line is prefetchable; and
aging the D-cache line with a delay if the D-cache line is unprefetchable;
wherein the D-cache line includes a demand stall flag, an aging flag, a history count and a reference count.
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Abstract
A method of providing history based done logic for a D-cache includes receiving a D-cache line in an L2 cache; determining if the D-cache line is unprefetchable; aging the D-cache line without a delay if the D-cache line is prefetchable; and aging the D-cache line with a delay if the D-cache line is unprefetchable.
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Citations
9 Claims
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1. A method of providing history based done logic for a D-cache, the method comprising:
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receiving a D-cache line in an L2 cache; determining if the D-cache line is unprefetchable; aging the D-cache line without a delay if the D-cache line is prefetchable; and aging the D-cache line with a delay if the D-cache line is unprefetchable;
wherein the D-cache line includes a demand stall flag, an aging flag, a history count and a reference count. - View Dependent Claims (2, 3)
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4. An integrated circuit device comprising:
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a processor core; a level one (L1) cache; a level two (L2) cache; an aging count in the L1 cache for indicating a number of least recently used demotions to be skipped between actual demotions to a D-cache line in the L1 cache, wherein the D-cache line includes a demand stall flag and an aging flag; a counter that counts each time the D-cache line is referenced in the L1 cache; and a comparator for comparing a history count to a reference count to determine when the reference count is equal to the history count for a D-cache line. - View Dependent Claims (5, 6)
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7. A processor device, comprising:
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a level one (L1) cache; a level two (L2) cache; circuitry configured to receive a D-cache line in the L2 cache, determine if the D-cache line is unprefetchable, age the D-cache line without a delay if the D-cache line is prefetchable; and
age the D-cache line with a delay if the D-cache line is unprefetchable;
wherein the D-cache line includes a demand stall flag, an aging flag, a history count and a reference count. - View Dependent Claims (8, 9)
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Specification